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ADS5263EVM / TSW1250EVM

Greg Bredthauer
Prodigy 100 points
Other Parts Discussed in Thread: ADS5263, ADS5263EVM, CDCM6100XEVM, CDCLVP1102

Hi,

I just purchased the ADS5263EVM and TSW1250EVM to give the new ADS5263 a try.  The evaluation has been rockier than expected, and I'd appreciate any assistance!

1) The ADS5263EVM has input SMA connectors labeled CLK_INP and CLK_INN.  I (wrongly) assumed that meant a standard differential LVPECL input clock could be used (such as the CDCM6100xEVM outputs).  My mistake there, but when I went to use an LVCMOS clock from the CDCM6100xEVM connected to the ADS5263EVM's CDCLVP1102, I found that SLAU344 does not mention that LVPECL biasing resistors must be added, nor is VAC_REF connected to INN, which seems to be necessary.  OK, this wasn't a question, but probably useful for others nonetheless, unless I'm missing something obvious.

2) I am providing a 100MHz clock to the ADS5263EVM.  I've installed the latest GUI software packages for the ADS5263EVM and TSW1250EVM, and connected them via USB.  Communication seems functional - I see things change when modifying registers in the ADS5263EVM GUI, and doing a "Capture Data" in the TSW1250EVM does indeed capture data.  However, the data is garbled.  When using the ADS5263 register settings called out in the user guide (page 12 of SLAU344), it appears that the upper and lower byte are swapped, and both upper and lower bytes have been rotated by 1 bit.  Thus bit 0 is coming out at bit 9, etc, both in the GUI and on the test headers on the TSW1250EVM.  I've confirmed this mapping by using the custom test patterns and setting a single bit at a time.  My best guess is that the TSW1250EVM's FPGA is not correctly deserializing the datastream from the ADS5263EVM.  Is there a particular sample rate I should be running at?  Is there newer firmware for the TSW1250EVM I'm unaware of?  The guide shows 80MHz in some of the screenshots, so I'll try that next.

3) The ADS5263EVM GUI debug function "Write Register" works.  However, "Read Register" always returns FFFF (even with Reg Read set to enabled on the first tab).  Is this a known bug?

Thanks in advance for any help!

-Greg

  • 0
    TI__Genius 12025 points

    1033.UserGuide_ADS5263_LCLKPhaseControl_4Oct2011.pdf

    6646.ADS5263 Test Procedure for Customers to Read.pdf

     

    Hi Greg,

    How are you?

    Thanks for using TI ADS5263.

    For the quick reply, first of all, I attached 2 files for you to double confirm if the test setup is the same as you are trying.

    Please notice that one register (Address=0x42, Data=0x8000) must to be set,

    that is the data output LCLK Phase setting when TSW1250EVM is used.

    For the Read Register option: On ADS5263 device itself, it has SDOUT pin#52 (page#6 on Data Sheet).

    On EVM board, this pin is only connected to a connector TP1 (page#28 on User's Guide).

    That is why you can not really read the register values (using the EVM)

    even though you try to run the GUI.

    Please let me know if you can receive the attached files or not.

    Please feel free to contact us again.

    Thanks and best regards,

    Chen

  • 0 in reply to Chen Kung
    Prodigy 100 points

    Hi Chen,

    Thanks for those documents.  I had already taken the other steps described, but writing 0x8000 to address 0x42 was new.  After taking that step, I'm afraid I still have some issues.  When capturing Channel A in the TSW1250 GUI, the upper and lower bytes appear swapped.  I was able to fix this by enabling I/O mapping in the ADS5263 GUI, and setting OUT1A to "CH1 - 2 WIRE" and OUT1B to "CH1".  I made similar changes for channels 2 - 4.

    The remaining symptoms/oddities:

    - When capturing a ramp, the captured values go up by 2 LSB per sample instead of 1 (note that I can now confirm that all bits are mapped correctly using the single custom pattern settings and setting a bit at a time).  Perhaps the TSW1250 is dropping every other sample?

    - Selecting channels A and B in the TSW1250 GUI and clicking "Capture" acquires believable results (mean ~32000DN, stdev ~1.04), but channels C and D return all zeroes.

    - The bits coming out on J5 on the TSW1250 PCB do not seem to correspond to the data being captured in the GUI (the documentation suggests it should, but perhaps that was only when used with the AFE* parts and not the ADS5263?).

    Thanks for your help,

    -Greg

  • 0 in reply to Greg Bredthauer
    TI__Genius 12025 points

    Hi Greg,

    Usually at the normal operation, we don't have to set the mapping.

    Here is another information (in the attached files).

    Please take a look and try it and see if you can capture the same data (including RAMP data).

    Of course, there could be other possibility.

    I will keep in touch with you again.

    Thanks and best regards,

    Chen

     

    6685.To Customer.pdf

     

    7356.ADS5263EVM and TSW1250EVM Test Results to Customers.pdf

     

     

  • 0 in reply to Chen Kung
    Prodigy 100 points

    Hi Chen,

    The only difference I see in the screen shots from those documents is the  TSW1250EVM firmware version.  My board reports:

    Firmware Type = 4

    Firmware Ver = 1.03

    Software Ver = 3.00

    Presumably I need to upgrade the firmware to match your results.  I have a Xilinx USB flash cable (and in fact I had begun writing my own firmware for the TSW1250EVM to see if I could work around these limitations).  Can you point me to a place to download the newer firmware from?

    Thanks,

    -Greg

  • 0 in reply to Greg Bredthauer
    TI__Genius 12025 points

    Hi Greg,

    Thank you for giving me very useful information.

    I will ask our test board design team for this.

    Also could you please send me email by:

    chen.kung@ti.com if it is easy for you.

    Thanks a lot.

    Best regards,

    Chen

  • 0 in reply to Greg Bredthauer
    Prodigy 100 points

    For future thread readers, my problem was indeed the firmware version on the TSW1250EVM I received.  Flashing it to version 2.02 resolved my problems.  Thanks Chen and Allen!

    -Greg