DAC5689 performance issue

Hi Tom,

   I have seen problems like that before on data convertors.  Some times I had to take the clock 10x slower.  When I saw things like that I suspected the timing in the time domain.  

Looking at the freq spectrum is OK, but first you have to get a good scope and look at the 2 clocks the data etc; see figure 16 and 17 in the data sheet.

We are talking about 2 nsec and a rise time of 0.2 nsec.  With the 49.9 ohms resistors that may affect the CLK timing.  Look at each signal and the output settling time.

Bruce, Thanks but here is the customer response;

Figure 16 & 17 ? deal with the serial interface; SDIO SDO SCLK.

I'm working in Half Rate Bus Mode : Figure : 32

CLK1 Th & Ts = 1ns; Which we are working with.

Comments please....

-Tom-

Tom,

The register settings is the correct setup for 1x int, dual clock mode, 400MHz DAC update rate. The CLK1 Ts and Th of 1ns minimum requirement is also met.

Other things that I would suggest looking also is the data source and the LMK clock source. Could the FPGA/ASIC timing changes with respect to temperature? One way to verify the DAC's functionality without the data source is use the constant input and NCO feature of the DAC. Use CONFIG4, CONFIG20, and CONFIG21 to enable the constant input. Then enable the NCO to program the output frequency. The constant input programs the amplitude (value depends on 2's complement vs. offset binary), and the NCO programs the output frequency. This test should help us narrow down whether the problem occurs at the DAC or DAC input.

When you mentioned the LMK04033 clock connection, is there any ac coupling between the clock and DAC clock receiver? I would recommend the customer to follow the LMK04033 LVPECL clock connection recommendation on Figure 13 of the datasheet. Use the 120ohm pull-down for emitter biasing. Instead of the 85/120ohm parallel resistor for biasing, they can replace them with 100ohm differential termination since the DAC Clock receiver has internal biasing (ac coupling is recommended). The clock amplitude may also affect timing and performance of the device.

Lastly, if you could provide schematic diagram, it would be helpful for further debugging.

-KH

KH,

Customer response;

The problem is the data interface between the FPGA and the DAC (CLK1), not with the output interface (CLK2) CLK2 / output works fine.
I can generate a tone out of the DAC without a problem, that was one of the first things I tried.

The problem only exists at the higher data rate.

DAC Temp Response : I can make this noise problem happen by just heating the DAC chip alone.  I placed a copper pad on top of the chip to distribute the heat and used a soldering iron at a 200F to heat up the DAC to revel the noise problem.  When the problem exists without heating up the DAC I can use freeze spray on the DAC alone to make it go away.

I have also delayed clocks and data to both the FPGA and DAC using the internal delays of the PLL & DAC and these had no effect on the temperature noise problem.
The only solution I came up with was to reduce the clock rate from 200MHz to 190MHz ( 400Msps to 380Msps ) ( Half Rate Mode using both DA & DB inputs ) and I was able to operate up to 60 deg C.

The question is what is the best termination to use for the CLK1 data input interface.
The clock supplying CLK1 is CLK_out2p/2n out of the LMK04033 chip which is (2P=LVCMOS & @N=Not-LVCMOS)  ...."LVCMOS" not LVPECL....
I've tried the single ended option for CLK1 & CLK1C as shown in Figure
38 and turned out to be worse than the initial LVCMOS differential option (2P=LVCMOS & @N=Not-LVCMOS).

-Tom-

KH,

In order to keep the schematics from this public forum, I have sent them to Fern Yoon of TI. Let me know if you need contact info. I believe Fern is tracking these posts.

-Tom-