length matching ADS61B49 DClock output and Data lines in the PCB design.

Hi,

how much length mismatch you could tolerate on your LVDS routing (or CMOS if that is what you are using) would depend on how much margin you have in your timing at the ADC receive interface in your FPGA or ASIC. 

You would check the datasheet to see what the guaranteed setup and hold time for the data around the clock edge would be (the datasheet lists timing for 170Msps, which is close, or you could interpolate between the listed timing for 170Msps and 150Msps).  If you use these timing numbers in the constraint files for your FPGA, then the static timing analysis tools for your FPGA would tell you how much margin (called slack) you have for your interface.

This margin tells you how much additional skew you could introduce between the clock and data before your timing became a problem.  Depending on the dielectric material of your circuit board, a signal travels approximately 6 inches in one nS, or alternatively an inch of length mismatch might equal approximately 160 pS of skew.  If you have about 160ps of margin in your ADC to FPGA interface, then you could tolerate about an inch of routing mismatch, for example.

We match the lenghts on our EVMs to about 5 or 10 mils, but that is because we have to room to do so and because we don't know what our customers may wish to do with the EVM. 

Regards,

Richard P.