The DAC5681 has an 8-deep FIFO in the datapath.
Register "OFFSET1" allows one to select the reset position of that FIFO pointer in bits 2:0 of that register. The description in the datasheet says:
You would expect this FIFO_OFFSET register to have a direct impact on the DAC output delay.
And that seems to be the case... more or less: when cycling through the 8 values, I see only 4 distinct output delays.
Apparently only the two LSBs of that register seem to have any effect: "+2" and "-2" cause the same delay at the output (010 and 110), just like +1 and -3 are the same, etc.
This is regardless of the interpolation setting (and I have the DAC_delay bits at a constant zero).
Note I am using a synchronous data interface (DAC data input clock == DAC output clock, so the FIFO pointer never moves after I program it with the FIFO_OFFSET register and then trigger a SYNC event)
I need to be able to shift the DAC output in at least 8 steps of one input sample in order to do per-pixel positioning of the DAC output. My controlling FPGA has a by-8 interface (8 samples per FPGA clock cycle) so I cannot to pixel-accurate positioning inside the FPGA without resorting to those horrible barrel shifters..
Is this a known issue with the DAC?
Or is this a "user error"?