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ADS1610 and RBIAS

Pavel Haintz
Prodigy 70 points
Other Parts Discussed in Thread: ADS1610

If I need to vary the frequency of the ADS1610 clock for different same rates, what value of RBIAS should be used.  The table in the data sheet specifies RBIAS values for fixed frequencies.  Do I set the RBIAS for the fastest frequency?

If I need different sampling frequencies, can the CLK be run through a clock divider implemented on a CPLD (not through a PLL)?  Or would this add too much jitter?

Thanks,

Pavel

  • 0
    TI__Guru**** 171186 points

    Hi Pavel,

    Take a look at figures 14, 15 and 16 in the ADS1610 data sheet (page 9 and 10).  At higher clock frequencies (beyond 9MHz), you begin to see the trade offs of RBIAS versus speed in the SNR, THD and SFDR of the ADS1610.  Figure 23 on page 11 also gives you an idea of the power consumption versus RBIAS.  Perhaps those figures can help you decide which way to go based on your end system needs regarding power vs. performance.  Table 1 on page 15 provides you with some guidance regarding jitter.  Using a  PLL is not necessarily required here, so depending on your input voltage and frequency, you might be able to get away with using the CPLD divider technique.