TSW3003 DAC5687 settings order for QPSK

 Greetings

I have not solve my problem yet.

Is my question correct?

May be I should reformulate it, or post it in other section, or smth else?

Best regards,

Alexander

Greetings

Really, no ideas, advice or response? 

Best regards,

Alexander

Hi Alex,

Apologies for the delay. My understanding is that the sample rate for the I and Q channel are 5MSPS each. You will provide 10MHz CLK1 for the interleave input.

With full-bypass mode, the final DAC update rate is also 5MSPS. With the on-board CDCM7005 of 491.52MHz VCXO, you may not be able to generate the 5MHz CLK2 needed for the DAC. You may need to change the VCXO to a frequency with even multiple of 5MHz, or configure the CDCM7005 in external clock mode as mentioned in section 9.2 of the user's manual.

Also, could you explain why you could not use pll_lock out in external mode? This is the mode that we typically use for evaluation. Could you use dual clock mode with FIFO as described in page 43 of datasheet?

-KH

Thanks for the reply

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As I see, my first problem is synchronization.

At first, I could not use pll_lock out in external mode,
because my FPGA (data signal source) had no (free) input
for external clocking of data output to the DAC.
Changing of FPGA Board is not possible now.

But I could use dual clock mode with FIFO.

Second, I should provide a same frequency for FPGA data output and DAC data input.
For example, 5 MHz (x1, x2, x3, x4, x6, x8, x16) for external VCOX of CDCM7005, as DAC data input.
or 491.52 MHz (/1, /2, /3, /4, /6, /8, /16) for FPGA data output.

What clocking frequency difference is allowed? (% or Hz)
For example, is it possible to use 491.51/16=30.72MHz for DAC
and 30.00 MHz for FPGA data sampling at the same time.

As I understand, if I couldn't use pll_lock out (that is the best variant)
then it would be better to set "same" clock frequences and use FIFO for synchronization.

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my second problem is DAC settings.

I used spectrum analyzer to control TSW3003 output,
while changing settings of DAC5687 and CDCM7005 I saw
that same elementary ections it TI USB Software for TSW3003 v1p1
not always give same results. (It was only twice and disoriented me)

It Looks like I provoke inner conflict (because I don't know some of internal DAC logic),
and to get result of "two steps previous"
I should reset all the board and start from the begining.

For this reason a asked about "settings sequence" from default state
For example: 1. Set "Full bypass" 2. Set "Interleave" 3. Set "Qflag" 4. Ses "2's Comp" 5. Unset "NCO" and etc.

Is it right, that for enterind simlest DAC interleaved mode? I should use only 1, 2, 3 from last example?

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Am I thinking the right way?

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Best regards,
Alexander

 Greetings

 Please, help me with some more answers

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How much the clock frequency difference can be? (% or Hz)
For example, is it possible to use 491.51/16=30.72MHz for DAC  input
and 30.00 MHz for FPGA data output at the same time

I will find FPGA board with SMA input for clocking later, and try PLL_LOCK out clocking for FPGA,
but in the case if FULL_BUPASS checked, there is no PLL_LOCK signal in " dac5687 external clock mode"

 I tried an Oscilloscope for the DAC output analysis, and noticed defferenci in A and B channel output
(settings are simplest and similar for both channels, just FIR_Bypass checked and NCO unchecked from default, non-interleaved mode, same input data)
And I got signal at the A channel output, "positive" and "negative" signals have same high/low levels (2 voltage levels total),
but in B channel "positive" signal has same low level as high level of "negative" signal (3 voltage levels total).
How can I fix it?

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Best regards,
Alexander

Any ideas?

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Best regards,
Alexander