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Unstable Clockout from ADS6242

bve
Prodigy 60 points
Other Parts Discussed in Thread: ADS6242, ADS6148, ADS6445

Hi, 

I'm working on a ADC module for an important customer and we are using the ADS6242 dual channel ADC together with a Spartan 6 FPGA. As the customer requires only 15MHz sampling rate for now, I configure the ADS6242 via SPI after power up and drive the Clock via Pin 18 and 19 with 15MHz LVDS from the FPGA. I can verify that the SPI transfer to the data registers works fine and the differential clock from FPGA to ADC is stable and well within 350mV differential levels. The device is configured for deskew testpattern (address 0x0A has only data bit 7 and 6 high), and 2 wire, DDR clock, 16x serialization with override bit active (0x0D has only bits 0, 2 and 10 high).

Problem:

However, when I measure the outputs DB0, DB1, DA0, DA1, Frame Clock and DCLK (Bit Clock), it shows big problems with the clock output from ADC to the FPGA. The frame- and bit- clock are not at all the same frequency as the sampling clock (or 4x in case of bitclock), they stop from time to time for more than 10 cycles or have missing or prolonged periods of low or high.

I managed to get it working from time to time, without a visible pattern and it was not reproduceable. I can't even explain, how the device can even generate this behaviour. Currently, we are thinking it might be a timing issue during the setup or even a problem with the internal PLL of the ADS6242. We have engineering samples from TI on the two prototypes and they are showing quite the same behaviour. Sometimes it works after loading the device configuration after power down for several minutes, then  we reload the configuration (without or with power down) and the faults with the DClk reapear again. The configuration via SPI had 5MHZ SPI Clock at first, i even reduced it to 500kHz without effect. Next to the ADS6242 is also an ADS6148, clocked with 150MHz and the same SPI component for configuration. The faster device works quite fine.

Any suggestions?

Best Regards,

Björn

  • 0
    Prodigy 60 points

    Here is an update:

    We measured the voltage on pin 3 "CAP", which is connected to the PLL and produces a saw tooth shaped signal with 32.8kHz and about 450mV peak to peak and its maximum at about 900mV. I guess it is a timebase for the PLL. This looks nice and steady. With the same low time resolution, we measured the bitclock again and can clearly see a correlation between the defective bitclock and the saw tooth. The bitclock produced generates about 1/3 of the period normal clock cycles, then stops in the next third and stays low with one or two spikes as exceptions, and stays high in the last third with exceptions of a few clock cycles at beginning of the last third and in the middle of the last third. The capacitor on pin 3 is connected to digital ground and is a 2nF, 25V, NP0 type with 5% tolerance, this is specified in the datasheet as well as in the EVM board.

  • 0 in reply to bve
    Prodigy 60 points

    Problem has been found, the PLL seems to be driven by LVDD, which is not just supplying the LVDS buffer. Since LVDD has to be in the range from 3V to 3.6V, the error occured due to undervoltage.

  • 0 in reply to bve
    TI__Mastermind 29220 points

    Hi,

    I'm glad to hear you found the issue.  I have been going through the datasheet (I don't support this device but I do support a very similar device) to see if i could find the likely source of the problem, but the two things that I suspected would not have applied to you, so I didn't have an easy thing to suggest.  Some of our devices have a register bit for slow speed operation, but this device does not need that so that was not an issue.  And wrong voltages on the four CFG pins would be a potential issue if you didn't have the Over-ride bit set. 

    But since both LVDD and AVDD for this device are supposed to be set to 3.3V, what voltage did you supply that there was an undervoltage situation?

    And by the way, the datasheet for this device needs to be updated for the recommended voltages for the CFG pins if you are not using the Override bit.  (Figure3 and Table 9,10,11,12) Compare these figures and tables to the corresponding portions of the ADS6445 datasheet on the web, and you can see that the recommended input voltages for the different settings have shifted some.  But that wouldn't matter if you are tying off these inputs and setting the over-ride bit.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 60 points

    We are using the ADS6148 in conjunction with ADS6242 on separate banks of the FPGA. While the faster ADS6148 needs 1.8V on its DRVDD, the ADS6242 was also powered from 1.8V via LVDD. This was a misconception and resulted in the described. However it is interesting, that from time to time it worked fine with 1.8V, until the next power cycling. I guess that no lower IO voltage is possible on ADS6242 because not only the LVDS buffers but also internal logic is driven by LVDD, or not?

    We strapped the CFG pins and configured the device entirely by SPI. In our application, we need some flexibility, so using the override is the only comfortable way.