I'm working on a ADC module for an important customer and we are using the ADS6242 dual channel ADC together with a Spartan 6 FPGA. As the customer requires only 15MHz sampling rate for now, I configure the ADS6242 via SPI after power up and drive the Clock via Pin 18 and 19 with 15MHz LVDS from the FPGA. I can verify that the SPI transfer to the data registers works fine and the differential clock from FPGA to ADC is stable and well within 350mV differential levels. The device is configured for deskew testpattern (address 0x0A has only data bit 7 and 6 high), and 2 wire, DDR clock, 16x serialization with override bit active (0x0D has only bits 0, 2 and 10 high).
However, when I measure the outputs DB0, DB1, DA0, DA1, Frame Clock and DCLK (Bit Clock), it shows big problems with the clock output from ADC to the FPGA. The frame- and bit- clock are not at all the same frequency as the sampling clock (or 4x in case of bitclock), they stop from time to time for more than 10 cycles or have missing or prolonged periods of low or high.
I managed to get it working from time to time, without a visible pattern and it was not reproduceable. I can't even explain, how the device can even generate this behaviour. Currently, we are thinking it might be a timing issue during the setup or even a problem with the internal PLL of the ADS6242. We have engineering samples from TI on the two prototypes and they are showing quite the same behaviour. Sometimes it works after loading the device configuration after power down for several minutes, then we reload the configuration (without or with power down) and the faults with the DClk reapear again. The configuration via SPI had 5MHZ SPI Clock at first, i even reduced it to 500kHz without effect. Next to the ADS6242 is also an ADS6148, clocked with 150MHz and the same SPI component for configuration. The faster device works quite fine.