DAC7821 Positive Voltage Supply

Hi Junheng,

The reference device generates  a positive 2.5V reference from GND. The negative reference is created by the level shifting of the reference. Since the output of the reference is forced to a virtual ground through the OpAmp, the only way for the reference to cope with this is to drop its GND pin to negative 2.5V.

As for the power supplies used for the OPA, the datasheet of the OPA277 suggests using (+/-) 5V for the supplies, which should be sufficient for your application.

The ideal reference would most likely be the REF5025, but you can probably get away with the REF5025A.

The DAC7821 lists its current consumption to a max of 5uA.

The OPA277 lists its current consumption to a max of 825uA per amplifier.

Keep in mind that these current consumptions are for the devices alone. When they are loaded or generating current these will be added to the demand of your supplies.

C1, the compensation capacitor that you mention, is recommended in order to minimize stability issues. These issues generally come from the parasitic capacitive between the leads of the OpAmp.  The compensation capacitor, is aimed to reducing the amount of ringing seen at the output of the OpAmp. The calculation for this compensation capacitor is fairly involved. In this case, a simplistic rule would be: The larger your parasitic cap load, the larger your compensation capacitor should be.

If you wish to calculate this exactly, you may want to take a look at this document.

http://www.ti.com/lit/an/sloa020a/sloa020a.pdf Look at part 7 Lead compensation.

This document goes into detail as to how to calculate the compensation capacitor.

If cap load stability is a concern in your application, using an OpAmp with larger GBW and larger capacitive load than the OPA277 will be ideal. The datasheet of the OPA277 shows a graph on page 8 that displays the amount of overshoot across different capacitive loads.

In order to help you some more with this issue I would need to know what capacitive load you would be expecting.

#EDIT

If you will be driving a large capacitance you may also need to look into some other compensation schemes.

Hi Junheng,

Unless you expect a lot of parasitic capacitance on the pins of your OpAmp a 3pF compensation cap should be enough.

You can observe parasitic capacitance from:

• Long traces
• Traces that are close to each other.
• Ground and power planes.

So inherently the recommendations would be, keep input leads as short as possible. Try to maintain other leads away from input leads, specially the inverting input pin. And finally, try to apply pour cut-outs for any planes going above or below the inverting input pin, meaning that no planes should be directly under or above the inverting lead of the OpAmp. If you expect to see inevitable parasitics, use a 5pF cap to stabilize the output.

Both devices perform really well at DC. What your your high frequency of interest?

Junheng,

I'm not very clear on what your application of these two devices will look like. Can you share a schematic or specific design goals? Are you using the DAC7821 in an attenuator application? (i.e. a signal applied at the reference input that is attenuated at the DAC output?). If that's the case, the DAC7821 does not include any output buffer circuitry on silicon, as is typical of multiplying DACs. The device is simply a digital interface and a trimmed R-2R ladder structure. With that in mind, there is nothing in place to purposely limit the bandwidth of the device, but parasitics on silicon will limit the device's bandwidth. This performance is summarized by Figure 8 in the datasheet and is inserted below:

As you can see from the plot, the devices performance as an attenuator radically changes over frequency, and at very high frequency it does not serve very well as an attenuator. 

If your interest is in using the DAC7821 to generate ac signals at 2MHz it certainly has bandwidth to create this signal but your precise requirements in terms of SNR, THD, and SFDR may require a DAC with a higher data rate. Additionally, you called out the OPA277 earlier in this thread - I'm not sure if you intended on using this device or not - but it's unity gain bandwidth is at 1MHz so you will not have good success using the OPA277 in this system.

Regarding the ADC in this system, generally speaking a delta-sigma ADC does have a very flat frequency response at near DC. As frequency increases the  response will remain relatively flat but there will of course be some roll off, it really depends on the filter architecture and I don't have any information on hand to describe what sort of digital filter is implemented with this device. There is some useful data in the typical characteristics section of the ADS1605 datasheet, though, that show pretty good SNR, THD, and SFDR results with F_IN of 2MHz. I do not support delta-sigma ADCs so it may be beneficial for you to post another thread requesting more information about the frequency response of the ADS1605.

The recommended circuit driving the input in Figure 11, the THS4502 is a very wide bandwidth differential amplifier with a unity gain bandwidth of 370MHz, the application circuit itself has a 3dB cutoff at approximately 12.45MHz. See below:

I hope this helps.

Hello Junheng,

I apologize for forgetting to cover your query about the bypass capacitors in my previous post. In general I like to use a parallel combination of a 100pF and 0.1uF capacitors on any analog supply rail. For digital supply rails I just use a single 0.1uF capacitor. The parallel combination is useful because it helps to overcome the performance of real capacitors that exhibit self-resonance properties that may allow for very high-frequency components to sneak into the analog supplies. This is still possible using the parallel combination but it widens the stop-band on sensitive analog supplies. It may be considered over-kill to use this parallel combination and should not be considered necessary, but 0.1uF should be included on all supplies at least.