ADS5281 ..

Hi, Sahitya

As you see the block diagram in page 1 of datasheet, A-to-D sampled data goes to a serializer that operates from 12x clock generated by the PLL and transmitted in LVDS DDR format. Based on the nature of LVDS format, the output of ADS528x can not be configured as singled-ended.

Thanks,

KW

Hi,

The output of ADS528x has octal channels and outputs are 12-bit given out by each channel is serialized in LVDS format. This means sampled digital outputs have to be stacked up to parallel bit by using active component such as FPGA's SERDES IP, not passive component. If you use only one channel out of 8 channels, you can set other pins floating to minimize FPGA pin interface. Please let me know if this works for you.

Thanks,

KW

Hi,

Basically, LVDS has differential in/output using positive/negative pins to FPGA interface, and this is the same interface to other FPGA vendors. The Xilinx app note says 1-wire and 2-wire DDR interface from ADC.  This is the way of ADC output formatting as still pairs. From this app note, ADC output data is serialized into one (1-wire mode) or two (2-wire mode) LVDS pairs per ADC. From 1-wire mode, bit clock has to be twice of 2-wire mode.

Thanks,

KW

hello kw,

read the above message first and get back to this message please...

here in above message i clearly told that i need to use less number of pins on fpga so that i can interface more adc's like 64 adc'c to one fpga ..my virtex 6  fpga i/o pin limited to 840 pins only ... according xilinx app note does it mean that each lvds pair is serialized to one wire ?? if yes then it solves the problem .... one wire per one channel ...... one pin/per channel enough on fpga ..is that true sir ???

did i go anything in wrong in that ..correct me please ...make sure u see before message also 

than you sir 

ur reply is greatly helping me sir ......

Hi, Sahit

That Xilinx app note does not give you how to translate LVDS to CMOS. Each of wire consists of differential (positive/negative) lines, and SERDES IP of Xilinx is supposed to get differential input. I found a LVDS-to-CMOS translator as below on the web. That might help you to minimize # of input to FPGA.

http://datasheets.maximintegrated.com/en/ds/MAX9111-MAX9113.pdf

Thanks,

KW

Sahit,

Single ended signals are not suitable for carrying the kind of data rate that you are looking for.  The ADS528x family can operate at sample rates up to 65Msps, and with 12bits/sample that makes for a data rate of up to 780Mbps.  That is much too high a data rate to transport over single-ended signals.  Normal CMOS-level single ended signals are usually good for up to about 200Mbps, maybe a little more.  Some single ended signal definitions such as HSTL or SSTL may be rated for more than that, but not for 800Mbps and our device does not output HSTL or SSTL.

The Xilinx app not that you referenced did mention a 1-wire or 2-wire interface but in that app note they are still talking about 1 LVDS pair or 2 LVDS pairs, *not* one signal pin or 2 signal pins.

If you are not using the data converter at its max smaple rate, but rather at something much slower, then the max data transfer rate for the serial data will be lower.  But you still would be limited to the max data rate that the FPGA single ended inputs could operate at.   I would contact your FPGA vendor to see what kind of data rate you could expect to support into your FPGA on single ended inputs, and work back from that.    For example, I just glanced through some Altera forums and I see that they have stopped publishing data rates for general purpose IO since it depends on so many factors, and instead they recommend you simulate a specific design to see if you can support the data rate you need.  But from one of the last times they did publish achievable data rates, I see this from a forum posting (http://www.alteraforum.com/forum/archive/index.php/t-21116.html):

General-purpose I/O standards such as 3.3, 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are capable of typical 167 MHz and 1.2 LVCMOS at 100MHz interfacing frequency with 10pF load.

That is a *long* way from supporting the kind of data rate from a device such as the ADS5281 on single-ended signalling.  You'll need the LVDS for that kind of data rate.

Regards,

Richard P.

Hey richard,

Thanks for the reply ..u explained things well ...there is no another way, my project is to decrease fpga count .... and coming to speed requirements my adc has to 65msps only so single ended outputs with that speed is not possible ...so i have to take  'u' turn in this regard....

anyways richard thanks for ur time ......