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ADS1606 ADC Questions

Randy Mitchell
Intellectual 330 points
Other Parts Discussed in Thread: ADS1606

If four ADS1606 ADC are tied to a common clock and taken out of reset at the same time, will all four ADC be in sync (phase)?

If four ADS1606 are running on a common clock, what is the best way to buffer / drive the clock? The spec sheet calls for a crystal osc to drive the ADC with as short of trace as possible. The application calls for running the clock thru a PAL to allow frequency changes and then driving the ADC. Is this fesaible? Thank you for your help in advance!

  • 0
    TI__Guru**** 172706 points

    Hi Randy,

    As long as the clock and reset signals meet min= -5ns and max= +10ns timing margin

    as shown in Fig. 3 and Fig.6 in the data sheet, then the multiple ADS1606 should be in sync. 

    You can use other clock source besides a crystal, and your clock skew should meet

    above timing margin.  You may use SN74LVC1G125 or SN74AHC1G as the clock buffer.

    Regards,

    John Wu