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DAC3164 - EXTIO Pin and Bypass Capacitors

kevin priest
Prodigy 160 points

Can the EXTIO Pin be left unconnected if not used? Or must it be connected to GND through a 0.1uF capacitor.

Also, the datasheet does not have any recommendations as far as the bypass capacitor network is concerned, nor does it mention anything about capacitance built into the package. I looked at the reference board and it appears to have an unusually high number of bypass capacitors on each rail and very large values at that, such as 10uF and to a lesser degree 0.22uF, which do not help decouple  in the 500MHz range that this part samples at. Is there a more proven decoupling scheme for this part which has been verified in the lab and contains not only a smaller number, but also more appropriate values for decoupling at the max sampling rate?

  • 0
    TI__Guru 68964 points

    Kevin,

    The EXTIO pin is connected to the internal bandgap reference, and we recommend the node to be bypassed with 0.1uF capacitor to ground for good filtering of bandgap noise. 

    Regarding the bypass capacitor network, there has been debates regarding different implementations. One theory is to implement multiple banks of different values of capacitors so the ESR/ESL resonance of the individual capacitor values are nulled out with the overall frequency response flat throughout the entire range. Another school of thought is to recommend the use of single value of multiple capacitors so there will not be any peaking due to resonance in case the ESR/ESL of individual capacitor starts to shift. 

    With the DAC being an switching element, any peaking in bypass network could cause performance degradation. This is based on my observation when the DAC output starting showing resonance spurs due to the oscillation of the LDO control loop when there are too "much" filtering network at the load of the LDO. The same should also apply to overall resonance response of the DAC power supply.

    The following article is also a good supporting document. The idea is to use the biggest capacitor network available to provide good bypass at low frequencies, and use the PCB power plane/ground stack-up as good bypass network for high frequency range.

    You can use your PCB tools to derive the via inductance and board capacitance. Also, you can use the capacitor manufacturer's datasheet to derive the ESR, ESL, etc. Once you have all these models, you can use TINA to simulate the impedance over frequency. See attached example.

    You may also refer to this article describing the use of biggest available value capacitors (in its size) to eliminate peaking due to ESR. The use of board capacitance for broadband filtering is helpful for high speed systems. The PCB board capacitance is the key to filtering out high switching speed at 500MSPS. 

    http://www.interferencetechnology.com/eliminating-the-myths-about-printed-circuit-board-powerground-plane-decoupling/

    Additional simulation discussion via TINA can be found in the following post:

    http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/p/198887/708951.aspx#708951

    I think the decoupling scheme for each system will be different depending on the PCB stack-up and via size. There is still a lot of investigations needed on this subject. 

    -Kang