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DAC5689 problem

hisakichi kobayashi
Intellectual 950 points
Other Parts Discussed in Thread: DAC5689

Hi all

There is a question by setup of DAC5689.

Table 5. Register name: CONFIG3 Address: 0x03, Default 0x00
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
    diffclk_dly(1:0)      clko_dly(1:0) Reserved
　　0 　　0 　  0     0     0     0     0     0
Although I am as mentioned above,
How is CLK2 set up if above-mentioned diffclk_dly is set as 1ns, 2ns, and 3ns?

Moreover, Figure28 of CLOCK MODE What does delta<t_align become?
For example, it is t_align=190ps when it is CLK1=112 MHz and CLK2= 672 MHz.
Unless it sets delta to less than 190 ps, can't it go then?

Moreover,
 diffclk_dly (1:0) is the function (0 or 1 ns, 2 ns, 3 ns) to set up the delay time of the input of CLK2/CLK2C (672 MHz).
 clko_dly (1:0) is the function to set up the delay time of CLK1 (112 MHz).
Is it what may be considered?


Best Regards,
Hisakichi Kobayashi.

  • 0
    TI__Guru 68544 points

    Hello Kobayashi-san,

    The diffclk_dly(1:0) and clk0_dly(1:0) are used to delay the CLK1 timing relationship with respect to the input data.  This allows adjustment of internal data setup/hold time if needed.

    CLK2 path is not affected.

    The diffclk_dly is used when CLK1 is configured as differential clock input mode. The clk0_dly is used when CLK1 is configured as single-end input mode. The choice of the setting depends on the diffclk_ena bit in Config2.

    Watanabe-san had posted additional information from your customer, I believe. I will look into his post and answer additional questions that he has.

    -Kang