Hi all,
I am using 3 ADS61B29 ADCs in my project. First one is getting an IF signal at 32.5MHz with a sampling clock of 50MHz. While the second one has 35 MHz input signal with 50 MHz sampling clock and the last one has 140MHz inpu signal with 200MHz sampling clock.
If I am giving an single ended input signal of 10dbm can anyone tell me the loss that happens at the input side of the ADC.
(Please refer Page number 43 - figure 64 and 65 of data sheet).
How is the impedance matching done in the input and clock side of ADS61B29?