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ADS61B29 input impedance matching and power loss

Other Parts Discussed in Thread: ADS61B29

Hi all,

I am using 3 ADS61B29 ADCs in my project. First one is getting an IF signal at 32.5MHz with a sampling clock of 50MHz. While the second one has 35 MHz input signal with 50 MHz sampling clock and the last one has 140MHz inpu signal with 200MHz sampling clock.
If I am giving an single ended input signal of 10dbm can anyone tell me the loss that happens at the input side of the ADC.
(Please refer Page number 43 - figure 64 and 65 of data sheet).
How is the impedance  matching done in the input and clock side of ADS61B29?

  • Hi,

    The ADS61B29 is desiged for a full scale range of 2.0V peak to peak differential, with some specified gain error.  So if you present a 2V peak to peak differential signal to the input pins then the output codes would span the full range.  Because there may be some gain error of a few percent, we usually back off the signal by 1 dB when evaluating the device.

    A 10 dBm sine wave into a 50 ohm load happens to be 2.0V peak to peak.  If you design for some other load, then 10dBm into some other load will be some other amplitude of swing.  The ADC is specified for input voltage, not power, so you have to consider the input power into some load and then see if the resulting swing fits the ADC requirements. There is no 'loss' of signal after it enters the ADC at these low input frequencies, or if there is then it is already accounted for when the device was designed for 2V full scale at the input pins.  You mention the example input drive circuit suggested in the data sheet, and that circuit *will* have some loss of signal through it.

    The two exmaple circuit diagrams in the datasheet represent something very similar to what we have on the evaluation module for the ADS61B29.  For bench evaluation we often use a sine wave from a high quality signal source, single ended from a 50 ohm coax.  In each of those example circuits, the single ended signal is converted to differential by transformer coupling.  Since the transformer coupling is 1:1 ratio, the 50 ohm input needs to be terminated into a 50 ohm load.  In figure 64 you can see the two 25 ohm resistors forming a 50 ohm differential termination.  The ADC inputs themselves are considered high impedance in comparison to the 50 ohm termination.  In Figure 65, two transformers are used for better phase and amplitude balance of the differential signal, but the impednace ratio through them is still 1:1 so a 50 ohm termination is still needed.  In this circuit, there is a 100 ohm differential termination (50 ohms + 50 ohms) after the first transformer in parallel with another 100 ohms differential after the second transformer for an effective termination of 50 ohms differential. 

    As for losses through the input circuit, the transfomer will have a datasheet spec from the manufacture and it is often 1 dB or less in the pass band of the transformer.  You would have to pick a transfomer and look up the specs.  And there will be a little signal dropped across the series resistors in figures 64 and 65 - but very little if the series elements are about 10 ohms total in this example and the input impedance of the ADC is relatively high. 

    The ADC will not accept a single ended input signal, so some signal conditioning will be required.  A transfomer coupling as shown in the datasheet is perhaps the cleanest approach, but other options are available such as using a fully differential amplifier device to condition the signal and drive the ADC.

    The clock input of the ADS61B29 is also relatively high impedance compared to an external signal source, so like the analog input it would need to be properly terminated external to the ADC.

    Regards,

    Richard P.