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DDC316 : Sampling without resetting?

James Masciotti
Prodigy 30 points
Other Parts Discussed in Thread: DDC316, ADS1274, IVC102

On the DDC316, is it possible to many consecutive samples in between consecutive resets? I ask because I would like to perform "up-the-ramp" sampling and essentially line fit my integrated signal in order to get the lowest noise measurement of my sensor's current signal. I would like to make up to 50,000 consecutive conversions of the input signal between consecutive resets.  Basically reset -> sample 50,000 times, reset again.

  • 0
    TI__Guru 62350 points
    James,

    What kind of resetting are you talking about? If it is resetting of the integration capacitor back to VREF, then no, we cannot stop this reset as it is fundamental to the device operation. Each cycle of A-side or B-side sampling must be reset before the next sample is taken.

    Regards,

    -Adam
  • 0 in reply to Adam Sidelsky
    TI__Expert 4620 points

    And just to add... although it is not necessarily the same, why wouldn't you just integrate longer? I guess we don't completely understand the question...

  • 0 in reply to Adam Sidelsky
    Prodigy 30 points
    Hi Adam,
    Thanks. I think I see that now.
  • 0 in reply to Eduardo Bartolome
    Prodigy 30 points
    Several reasons having to do with lowering noise and expanding dynamic range. In many applications its about the trade-off between SNR and acquisition time, where people try to maximimize SNR/sqrt(time) in their design.
    When ever using one of these charge amplifiers, there is a random residual voltage left on Cf when Sref opens. This "reset noise" is inversely proportional to sqrt(Cf). If I could sample right after Sref opens, and at the end of integration and then subtract the first sample from the second, I would immune to this reset noise. This is called correlative double sampling (CDS), and although I am immune to reset noise, I had to take 2 measurements whose electronic "read noise" now adds orthogonally and so my total read noise has gone up by the sqrt(2). If I could take Many (N) samples by taking Np samples at the beginning of integration and Np samples at the end of integration, and subtract the average of the first Np from the average of the second Np, then I could reduce the read noise by a factor of sqrt(Np/2) or sqrt(N/4). This is called Fowler sampling. Furthermore, if I wanted to fully utilize my exposure time, I would take N samples through out integration and use this to do a least square fit to a line. This would reduce my noise by a factor of sqrt(N/12) which is not as good as fowler, but has the added benefit of being able to take as many samples as possible before saturation. If saturation is possible, it make it difficult to implement fowler or CDS, but with this "up-the-ramp" sampling one can always be sure to be able to effectively measure the very large currents that saturate quickly, and still be able to make low noise measurements of non-saturating and small signals, and thereby maximize dynamic range. We have done this to great effect with one of your other products the IVC 102. We use the IVC102 with a differential amp and a 24-bit adc (ads1274) to take 50,000 samples per second during an integration. This allows us to measure currents ranging from less than 1 fA to 1 uA in a single integration (we call it an exposure, since we are measuring light). The DDC116 has the advantages of having lower baseline noise than the IVC102, less susceptibility to external noise and smaller footprint due to being a single chip solution. If I was able to take 100,000 samples per second with the DDC116 and use up-the-ramp sampling I might have been able to reduce my noise for a 1 second exposure down to less than 10 attoAmperes, while still being able to measure larger 300 nA currents.