This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC37J82 register setting sequence

Other Parts Discussed in Thread: DAC37J82, LMK04828, LMK03033, DAC37J84


    can you help me to confirm the question:

      may i configure the all registers in the order from config0 to config105,when setting DAC37j82 registers ?

  • Hi Allen,

    You can program the registers in any order. The key to the DAC37J82 register is the alarm checking (i.e. such as PLL lock status) and the initialization sequence (i.e. 0x4A JESD204B intialization registers).

    You may see the document link below for detail. This will be going to the latest DAC37J82 datasheet update 

    4212.0116.DAC38J84 Start-up Sequence.docx

  • hello Kang,
    Thanks for your quick response.
    I have another question: how to calculate the DAC clk、 JESDclk and SERDES clk of DAC37j82? what is the computational formula of these clock?
    my configuration : DAC37J82_2x_250MData_2lane_222mode_Fdac1000MHz_onchipPLLenable_inputclock250MHz.
    look forward your reply.
  • Hi Allen,

    You may download the DAC3xJ8x EVM GUI. The main page provides all the calculation for the clocks, and the low level page tells you the equivalent register settings

  • Hello Kang,

    Can I see the register change in low level view when I change something on GUI while not connected to actual EVM board?

    Load/Save config is supposed to work without connection to EVM?
  • Hello Jin,

    Yes, the GUI has a simulation mode that can work without an actual EVM board connected to the PC. In the simulation mode, you may view each register changes in the status log. Simply double click on the lower left hand corner and the status log will show up.

    You may always load the register config file. The saving config feature works intermittently in this version. After you save, you may want to reload again to make sure it saves correctly. 

    here is an config file that you may try:


    The file description can be found in the following post:

  • Thank you. It helped a lot. 

    I have one more question for you.

    Now I detected alarm. I have no idea where it's from.

    So I reset all alarms mask bits (set all 0 for config4, config5, config6).

    But still alarm pin goes high.

    If I reads out registers for alarm, it's as follows

    I disabled DAC pll and uses only 4 lanes.

    register 100 : 0x0000

    register 101 : 0x0000

    register 102 : 0x0000

    register 103 : 0x0000

    register 108 : 0x0007

    register 109 : 0x0000

    Any thoughts?

  • Jin,

    To mask the alarms (i.e. alarms on register config100 to config109 do not show up on ALARM CMOS pin), you should set the alarms masking to "1b'1" in config4, config5, and config6.

    To unmask the alarms (i.e. alarms on register config100 to config109 show up on ALARM CMOS pin), you should set the alarms masking to "1b'0" in config4, config5, and config6.

  • Kang,

    Thanks for clarification. 

    Now I can control the alarm pin. The next step is do JESD pattern test. 

    FPGA JESD core can send test pattern like /D.21.5/, /K.28.5/ etc.

    While I'm doing that test, what registers should be checked to make sure if it's working?

    I've checked config100~config109 and they are all 0 except config108 (it's read back as 0x7). 

    I uses 4 lane only and don't use DAC pll. So I thought it's working fine.  But after changing test pattern to which different from FPGA, The register values of config100 ~ config109 are the same. ??  

  • Jin,

    You may refer to the end of the following post for instructions of the JESD204B pattern test with Altera FPGA. This is a transport layer test so you have to make sure the physical layer (SERDES level) have to work fine.

    It is basically part of the interop report.

    For physical layer variation, refer to earlier part of the discussion for tests such as PRBS.

  • Kang,

    According to DAC datasheet, I can select and check internal data. 

    But I couldn't find any details for jesd_testbus_sel in the datasheet. 

    Could you help me out how to set up and which pin I need to check?

    The following is from datasheet page 52(dac37j82.pdf).

    Users can select to output the internal data (ex, the 8b/10 decoder output, comma alignment output, lane
    alignment output, frame alignment output, descrambler output, etc ) of a JESD link for test purpose. See
    jesd_testbus_sel for configuration details

  • Hello Kang,

    I have one more question for you.

    I'm trying to test JESD data link layer with test pattern for example K.28.5. 

    According to datasheet, DAC will verify test pattern and report to alarm. 

    But I have no idea which register I should check.

    The following is taken from datasheet. 

    Could you let me know which register has pass/fail test result? 

    jesd_test_seq Set to select and verify link layer test sequences. The error for these 00
    sequences comes out the lane alarms bit0. 1= fail and 0 = pass.
    00 : test sequence disabled
    01 : verify repeating D.21.5 high frequency pattern for random jitter
    10 : verify repeating K.28.5 mixed frequency pattern for deterministic jitter
    11 : verify repeating ILA sequence

    Thank you.

  • Hi Jin,

    Regarding the link layer test sequence:

    Enable the link layer test pattern through register jesd_test_seq in config74 (0x4A). Once the associated pattern is transmitted from the JESD204B TX logic device for the link layer pattern test, the error will be reflected on bit 8 of config100 to config107 for the respective JESD204B RX lane.

    I have send this information to our tech write for the datasheet update.

  • Jin,

    The JESD_testbus_sel is meant to be a TI internal test only. The output of the internal data may not provide much meaningful result in terms of debugging your system. We are removing this from the datasheet moving forward.

  • Hi Kang,

    Thanks to your help, I'm making progress. 

    I did JESD pattern test like K28.5 or D21.5. 

    As you mentioned I could check pass/fail bit on config100 ~ config103 bit 8(use 4 lanes only).

    But I got Lane0~3 FIFO error (bit 3=write error : asserted if write request and FIFO is full).

    I have no idea what it means. 

    Do you have more information on that error? What causes that error?



  • Jin,

    You may ignore the Lane0~3 FIFO error during JESD pattern tests. You should only consider the FIFO error during normal operation of the DAC37J82. There is a FIFO stage between the JESD204B RX block and the digital logics of the DAC37J82. If the data rate between the two stages are mis-configured, the FIFO error will trigger.

  • Hi Kang,

    JESD pattern test passed. I'm working on normal operation, but I couldn't see any data output from DAC.

    I did DAC core test as described in somebody's post. I could see f/8 sine wave as expected. 

    But while I'm doing normal operation, I got FIFO error and no data output from DAC.

    I have a couple of questions.

    1. JESD clock : I couldn't find any information of how it's used and what value should be set.

    2. According to DAC37J82 datasheet. M value seems fixed as 2. is M value configurable? Can I use 1?

        Currently tx sends M value as 1 so I asked to change that value to 2.  I tested with M values as 1 but got the same result.

    If you have anything for me to check or try to figure out FIFO error, please let me know.



  • Jin,

    Let me look into this and get back to you.

  • Jin,

    The JESD clock is the clocking provided to the JESD204B RX logic. The following listed the pre-determined divider setting in config37, bit15 to 13

    The M value is fixed. The predefined LMF mode for DAC37J82 are 821, 421, 222, and 124 modes.


  • Hello Kang,

    Thanks to your all support, DAC works now.

    I have one more question regarding DAC setting.

    At first I tried to test with DAC clock as 108 MHz and multiplier as 20. 

    But it didn't work. To make it work, I had to increase DAC clock as 216 MHz and set multiplier as 10. 

    Serdes line rate is 2160Mbps and Serdes reference clock is DACCLK. I think both setting should work. 

    Could you explain why the first setting(108MHz, 20) didn't work?

  • Hi Jin,

    With higher multiplication ratio and lower reference clock frequency, the SERDES PLL are more sensitive to input reference clock jitter. I suspect by moving the reference clock from 108 to 216MHz the jitter performance becomes acceptable. We provide our DACCLK from high quality clock source such as the LMK04828. Please double check your clock source performance and maybe we can narrow it down.

    We can also duplicate the setup here to see how 108MHz reference works for 2160Mbps of SERDES rate. I believe you are using the follow mode, please let me know if I misunderstood your setup:


  • Hi Kang,

    I'm using LMK03033 clock chip instead of LMK04828.

    Could you check that's the reason I got that issue?

  • Hi Jin,

    I am not too familiar with the LMK03033, you can check with the clocking team on the clocking forum for their advise on this.
    We can only check the setup with the on-board LMK04828 on our DAC EVM.

  • Kang,

    No problem. I will check clock forum if I have any question for clock chip.

    I have one issue with DAC37J82, I got sysref errors (check register 108). 

    I'm using 4 lanes and got this error from 2 lanes.

    The following is the current alarm and error registers.

    I don't use DAC PLL and SERDES PLL1 so I think we can ignore the alarm on register 109.

    register 100 : 0x0000

    register 101 : 0x0000

    register 102 : 0x0000

    register 103 : 0x0000

    read register 108 : 0xc007

    read register 109 : 0x0ff0

    What does sysref error exactly mean? When does it count?

    I tried different sysref setting(register 0x24, 0x5c) but got the same error.

    I've attached my configuration file for your reference. 




  • Hi Jin,

    There is an error on the datasheet description and we are working on the datasheet update (it is scheduled to be completed by mid 2nd quarter)

    for config108, 15:12 alarm_sysref_ err, each bit should be refer to link SYSREF error as oppose to lane error.

    bit15 = link3

    bit14 = link2

    bit13 = link1

    bit12 = link0

    The DAC37J84 supports up to two independent JESD204B links (link0 and link1) Each link can have up to 4 lanes as long as the number of lanes in each link matches. The lane to link mapping is done in config73.

    If the read back of error for these 4 bits are 0xC, then link1 and link0 do not have SYSREF error. By default, only link 0 is used. Link 1 is used in combination of link0 if some redundancy is needed in the system


  • Hi Jin,

    I have confirmed on our TSW14J56 + DAC37j82 EVM that with quarter rate SERDES, the reference clock of 108MHz, multiplier of 20x would work. I also confirmed the two additional mode:
    1. half rate, 10x multiplier
    2. full rate, 5x multiplier
    The clocking solution is done via LMK04828, clock buffer mode.
  • Kang,

    Thanks for clarification. So I don't need to worry about that errors.