DAC37J82EVM to KC705 simple startup from JESD204B TI reference design

we will look into this and get back to you.

Andrew,

Are you trying to use HSDC Pro GUI with the KC705? If not, the TSW14J10 is not needed. All of the DAC register settings are done through the DAC GUI. The TSW14J10 allows JESD204B parameters to be written to the FPGA when using HSDC Pro GUI. How are you setting up the JESD on the FPGA? Are you also enabling the second clock out of the DAC EVM that is required by the JESD204B IP? If not, the link will not work. The only source code we have for the FPGA is what is available on the TSW14J10EVM product folder.

Regards,

JIm  

Hi Jim,

I'm not using the HSDC Pro GUI in this case. I tried it before and was able to view sample waveforms but now I need to connect directly to the DAC via the KC705 in order to implement some custom VHDL/Verilog.

Sorry, I don't have a lot of experience with JESD. So far, I've been stuck trying to setup the JESD using the tsw.c program in the TSW14J10EVM product folder. I was hoping there would be a start up sequence for setting up the JESD parameters. I see on page 22 of the JESD204B TI reference design pdf that there's a setup process but I didn't find it anywhere in the code.

It says in the pdf that the HSDC pro uses bistreams generated using this reference design, do you have a version of the reference design that isn't abstracted by HSDC pro so that I can view how to setup the registers and send sample data?

Andrew

Hi Jim and Kang,

Any luck with my problem? Any help is appreciated.

Andrew

Andrew,

In the TSW14J10EVM product folder, click on the Xilinx firmware Source link shown below to get the source code. This is a project you need to compile first following the instructions in the document that comes with this firmware. After you do the compile by running a script file, you will have source code you can then view. The document also talks about JESD registers and how to program them using the Xilinx tool set.

Regards,

Jim

Hi Jim,

I've already built and compiled the xilinx project using build_it.tcl script. The source code you're referring to is the same one that I've been referring to I believe, tsw.c. Is this correct? Also, can you elaborate on how to setup the JESD registers for the DAC37J82EVM? I've read the document that came with the TSW14J10EVM xilinx firmware source but it doesn't state what registers to set for this DAC in what order.

Andrew

Andrew,

We can provide you with a configuration file that will load all of the registers on the DAC37J82EVM after you provide us with the following information:

1. DAC input data rate

2. Interpolation value

3. Number of JESD Lanes

4. Is the EVM setup for internal clock mode or external?

5. K value

6. Number of DAC's used

7. Number of samples per frame (LMFS mode you plan on using)

Regards,

Jim

Hi Jim,

I don't mind setting the registers in the DAC via the DAC GUI (which are

Dac input data rate: 368.64MSPS
# of SERDES: 4
Interpolation: 1
onboard EVM clocking
1 DAC
the LMFS i was using in HSDC is 4211
and I'm not sure of the # of JESD lanes and k value).

My immediate concern is how to talk to the DAC once I've configured it using the DAC GUI.

Andrew

Andrew,

What do you mean by talk to the DAC? This is what the DAC GUI does. Or do you mean how do I send the correct JESD204B digital data to the DAC?

Regards,

Jim  

Hi Jim,

Yes, how do I send the correct JESD204B digital data to the DAC from the KC705 using your reference design found in TSW14J10EVM project folder?

Andrew

Andrew,

To send the correct data, you must use the TSW14J10, HSDC Pro GUI, and follow the example in the TSW14J10 User's Guide section 6.1. HSDC Pro GUI has and loads the firmware (svf file) required by the FPGA for this test.

Regards,

Jim

Hi Jim,

So then there's no way to interface the KC705 to a DAC37J82EVM without using the interposer board?

Andrew

Andrew,

If you want to interface the KC705 to the DAC without the interposer board, you will have to create your own custom firmware that may or may not use the Xilinx JESD204B IP core and you will have to generate software to load the desired data to the FPGA that has to be sent to the DAC across the FMC connector. Some customers do this but it requires a lot of work and personal on their end.

Regards,

Jim

Hi Jim,

I see, so then how is this reference design supposed to be used? After generating the bitstream using the tcl file, what is the next step?

Andrew

Andrew,

The next step would be to take the project file that was created by the script and remove the HSDC Pro interface section with your custom firmware that will provide the new interface to the JESD204B Core. This includes writing to the registers that control the JESD as well.

Regards,

Jim