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Acquisition Time of ADS1115-Q1

Other Parts Discussed in Thread: ADS1115-Q1


Dear, All

The customer has three questions.
(1) Please tell me Acquisition Time of ADS1115-Q1.
    Data rate which they use is 860sps.
(2) Does Acquisition Time become long if I slow Data rate?
(3) Please tell me the value of の Ca1/Ca2/Cb Figure 24 listed in data sheet P13.
    The FS mode which they use is a mode of +-0.256V.
Because they want to put a filter in analog input, it is a purpose to check the influence.

Thanks, Masami M.

  • Masami-san,

    1. The acquisition time is the entire time of the data period. In the case of 860SPS, the acquisition time 1.163ms. The ADC will use the entire period to take the data.

    2. If you use a slower data rate, then the acquisition period becomes longer.  At a data rate of 8SPS, the acquisition period is 125ms. There is no sample and hold and the ADC behaves like a delta-sigma type converter.

    3. The equivalent resistance shown in the figure comes from periodic capacitive sampling. The equivalent impedance is equal to the sampling period divided by the capacitance. At a full scale of ±0.256V, the equivalent resistance is 710kΩ. This means that this differential impedance is equal to (1/fCLK)/CB. With fCLK = 250kHz, CB becomes 5.6pF. With the common-mode impedance, it is listed as 100MΩ for this range, This makes CA very small or 0.04 pF.

    Joseph Wu


  • Hi, Joseph-san

    Thank you for your answer.
    However, I ask you a question again for (1),(2).
    About "7.3.2 Analog Inputs" of P12 of the data sheet.
    There seems to be "the sampling phase" while S1 is closed and "the discharge phase" while S2 is closed in Tsumple time.
    In other words, I think that the period to close S1 is shorter than Tsumple.
    Please tell me.

    Thanks, Masami M.

  • Masami-san,


    S1 and S2 are closed for the same amount of time. They are both turned on and off at a rate of 250kHz and come from the same clock, but are inverted and non-overlapping. It takes many samples with this switch setup so that you get 1 output data. At 860SPS it takes about 290 S1/S2 samples to get output data.

    In my previous post, I mentioned that this converter behaves as a delta-sigma data converter. It will take many samples to get each output data.


    Joseph Wu


  • Hi, Joseph-san

    I thank for your support.
    I calculate "turn on" time with a period of 250kHz in 2uS.
    When Data Rate slows it from 860sps, may I think with turned on and off at a rate of 250kHz?

    Thanks, Masami M.

  • Masami-san,


    When you ask ask about the "turn on" time, are you asking about the extra time needed to start up the ADC when used in single shot mode? This start up time is about 20us. Please note that the data rate has a ±10% variation and this additional start up time will not add much time to the actual conversion.


    Joseph Wu


  • Hi, Joseph-san

    I thank for your support.
    A customer watched after the input filter, the input voltage of ADS1115-Q1.
    After fixing AIN3 to 2.7V, and confirming AIN2 in the range of +-200mV, straightness of around +-50mV was bad.
    It was a purpose to have wanted to know On-time of S1 to check the reason.
    In addition, there is about 30uV in a straightness error at around +-50mV, in the case of the input resistance is 10kΩ, and there is few uV in a straightness error at around +-150mV.
    In the case of the input resistance is 1kΩ, a straightness error was about 10uV at around +-50mV.

    Thanks, Masami M.

  • Masami-san,


    Using large filter resistors will cause the non-linearity that your customer is seeing. For the ADC, the input is repeatedly sampled with a capacitor. Putting a large resistor in the input path will disrupt the sampling with the capacitor. For larger input voltages, you may not see this effect, however with smaller and smaller input voltages, this sample disruption may cause a non-linear measurement.

    In general, I recommend filter resistors smaller than 5kΩ, but this may depend on the precision needed in the application.

    So yes, the input filtering will cause this non-linear measurement. It is a result of the input resistance reacting with the sampling capacitor and is influenced by the sampling period in the ADC.


    Joseph Wu
  • Hi, Joseph-san

    Thank you very much for your reply.
    I understood it.

    Thanks, Masami M.