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ADS131A04 synchronous slave mode DRDY imput pulse timing details

Jani Okker
Expert 3010 points
Other Parts Discussed in Thread: ADS131A04

Hi,

I've been thinking different options for a case where there might be one or optionally two ADS131A04 and those needs to be synchronized. This is a case where there always is one analog input daughter card present, but then optionally there might be also second daughter card installed. I first thought that from system perspective perhaps easiest to manage would be to use both in synchronous slave mode. However I did not find from datasheet that how accurate the synchronization pulse on DRDY input must be related to CLK_IN to avoid resynchronization / filter reset. 

I found a thread 

https://e2e.ti.com/support/data_converters/precision_data_converters/f/73/t/540737

 where it can be interpreted that this pulse actually needs to be exactly on correct CLK_IN edge. Is this correct or is there any range when the pulse may be given without resetting the filters. Also what is the maximum length of this pulse, is it one CLK_IN cycle? Datasheet says also that "In synchronous slave mode, DRDY is an input signal that must be pulsed at the device set data rate".  So if would give just one falling edge to to DRDY for devices to be sychronized and then keep signal low, would that also cause resynchronization fault? (of course in this case it could happen that some data is missed when reading is not keepin in synch, but that would not be that serious as resynchronization fault).

I was just wondering that if it must be very exact and ADCs are running on different clock than controlling host, then reaching a system with where all ADCs are in synchronous slave mode and there would not happen resynchronization faults will be hard. 

  • 0
    TI__Mastermind 38745 points
    Hello Jani,

    When the ADS131A04 is configured in Synchronous Slave Mode and DRDY is an input, the DRDY input falling edge must be between the falling CLKIN edge of the last clock from the last conversion cycle and the falling CLKIN edge on the next cycle. This means you have 1 CLKIN cycle to input DRDY and have the device remain synchronized. Of course you must also observe the setup/hold times for the pins for it to be a valid input.

    To answer your question regarding holding DRDY low, yes this would trigger a re-synchronization.

    If your host and devices are running asynchronously, let me suggest an easier option. Run the first device in Asynchronous Interrupt Mode and the second device in Synchronous Slave Mode with the same CLKIN. Then connect the DRDY output from the first device to both the host's interrupt pin and the second device's DRDY input. That way the devices will remain synchronized.

    Regards,
    Brian Pisani