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DAC5670: DAC input code and output swing NOT matched

Part Number: DAC5670

Hi,

I'm having trouble with DAC5670 device.

The amplitude of output signal does not match the input code.

And I can't get large enough output signal whatever code I input to the DAC.

To separate this issue from any other possible sources, I did the following:

- I designed 2 registers in the FPGA and connected each register's output to DA bus and DB bus.

- If I write value_A to register A and value_B to register B, then the input code to the DAC should be alternating value_A and value_B. (value_A,value_B,value_A,value_B,...)

- By doing this, I can ignore the setup/hold timing issue of DA, DB input bus.

Then I tried to write the registers as following steps:

1. value_A = 0x0, value_B = 0x0001

2. value_A = 0x0, value_B = 0x0002

3. value_A = 0x0, value_B = 0x0004

4. value_A = 0x0, value_B = 0x0008

5. value_A = 0x0, value_B = 0x0010

6. value_A = 0x0, value_B = 0x0020

7. value_A = 0x0, value_B = 0x0040

8. value_A = 0x0, value_B = 0x0080

9. value_A = 0x0, value_B = 0x0100

10. value_A = 0x0, value_B = 0x0200

11. value_A = 0x0, value_B = 0x0400

12. value_A = 0x0, value_B = 0x0800

13. value_A = 0x0, value_B = 0x1000

14. value_A = 0x0, value_B = 0x2000

15. value_A = 0x0, value_B = 0x3FFF

In my opinion the output signal should be doubled as the above test proceeds, but it isn't.

The output signal gets larger until value_B=0x0100. But things are getting strange from the following steps.

When value_B=0x0200, the output signal becomes as small as the signal when value_B=0x0020.

When value_B=0x0400, the amplitude is the same when value_B=0x0040.

When value_B=0x0800, the amplitude is the same when value_B=0x0080.

When value_B=0x1000, the amplitude is the same when value_B=0x0100.

I have double-checked the pin assignment of the schematic and FPGA constraint many times.

There are 2 DACs on each board, and we have 4 boards so there are 8 DACs on our hand, and all 8 DACs have the same issue.

Do you have any idea to solve this problem?

FYI, the datasheet I have is ()

  • Hi Nathan,

    I am looking into the your question. I will respond back tomorrow.

    Regards,

    Neeraj Gill

  • Hi Nathan,

    Can you please describe how you are looking at the output? Single ended or differentially? Can you please send me your schematic showing how the IOUTN and IOUTP are terminated?

    Can you please tell me what is your Rbias resistor's values and also check if it has been soldered properly? Also make sure sleep pin it tied low.

    Also can enable DLL and try to see if it makes any difference?

    Regards,

    Neeraj Gill

  • The way I'm looking at the signal is to connect the output port(P4) and oscilloscope through 50Ohm coaxial cable - single ended.

    The above schematic shows how the output signal is terminated. And Rbias is 2kohm as you can see in the picture. They are soldered properly.

    Sleep and other control signals are connected to FPGA and are controlled as follows:

    - DA, DB bus: connected to registers for test.

    - NORMAL: High

    - LVDS_HTB: Low

    - A_ONLY: Low

    - A_ONLY_INV: Low

    - A_ONLY_ZS: Low

    - RESTART: Toggled high to low during boot and stays low

    - SLEEP: Low

    - INV_CLK: Low

    DLL is already used and LOCK signal indicates high.

  • Hi Neeraj,

    I found what caused this issue.

    We assembled a wrong balun device. The circuit of balun we had used was completely wrong.

    We changed the balun, and now everything is OK.

    Sorry and thank you very much for your support.

    Nathan