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ADS8332: The analog input pin has unusual voltage

Part Number: ADS8332
Other Parts Discussed in Thread: OPA320

Dear all

Right now I'm using ADS8332 to sample 8 different voltage signals. The schematic is as below. Input use 200ohm, 100nF filter network. External reference is 4.1V, VA is 5V, VBD is 3.3V.

When I remove all the 200ohm resistors, I find that all the analog input pins from IN0 to IN7 all has very stable DC 1.6V. I don't know where this voltage comes from. Is it generated by the ADC itself? Could you please help to answer this? Thanks a lot.

And also, I have a question about the unused pins of ADC's analog inputs. Should I just terminated the unused pins to ground with capacitor?


  • Hi Feng,

    The ADS8332 is a SAR ADC and Multiplexer, where the internal equivalent circuit is shown in the diagram below.  The structure consists primarily of the internal Sample-and-Hold switch, the sample and hold capacitor, the multiplexer switch, and internal ESD structures.  

    When the input are left floating, there is no internal circuit driving the sample-and-hold; only small parasitic leakage currents of the internal ESD structures and internal circuitry are present.  In general, the sample-and-hold of the ADC tends to store the charge (or voltage) of the last conversion.  On the unit tested on the bench, when leaving the inputs floating, the first conversion tends to be close to zero volts; although the voltage is not well defined and may drift.

    Best practice is to terminate the unused pins to GND with a resistor.

    Thank you and Best Regards,

    Luis Chioye

  • Hi Louis

    Thanks for your replying. But I just leave the input terminating to GND with caps, when system is powering up, there is indeed an stable DC voltage at INx, I can hardly find the charging path for these caps, cause there is no input signal. And when reading back the ADC's results, it is the same as the input voltage. Can you provide some suggestions for this?
    And it seems that the cross interference may mainly come from last channel's last conversion. Do you have some suggestion that I can make the sample and hold cap discharge faster? And if the voltage on IN0 is higher than the next channel IN1, then IN1's converting results might be higher than actual value. If we add buffer between MUXOUT and ADCIN, will this cross interference be solved? Are there some other solutions for this?

    Feng Luo
  • Hello Feng,

    - The unused inputs need to be terminated with a pull-down resistor (1kOhm) to GND.  Capacitors do not provide a DC path to GND.

    The ADS8332 is a SAR ADC and the device needs to be driven with a low impedance source or driving circuit.   The driving circuit needs to be carefully designed to charge or discharge the internal sample and hold capacitor and settle to the target voltage within +/- 1LSB of the 16 bit resolution during the allowed acquisition period.  Therefore, the amplifier and RC driver circuit needs to have enough bandwidth and must be carefully designed to settle within the acquisition period. The acquisition period is dependent on the sampling rate and mode of operation of the device. The Applications Section of the datasheet provides examples of driving circuits for different sampling rate requirements in some detail.

    - For example, if you require to scan channels at maximum throughput, the circuit of Figure 53 is recommended, using OPA320 buffers at each input of the multiplexer.  In this example,  the device in set in Manual-Trigger mode, running at 500kSPS, with auto nap disabled where the acquisition period is ~350nS. The OPA320 (GBW=20MHz)  driver amplifier and R=40Ohms and C=1.5nF  is able to completely charge and discharge the sample and hold to the target voltage and settle to the16-bit resolution as the device scan through channels.

    - For lower throughput applications, using a single amplifier between MUXOUT and ADCIN can be used as shown on Figure 55. Placing an amplifier as a buffer between the multiplexer output and the ADC input helps to relax the requirements of the driving circuitry at the INx multiplexer inputs. Since there is still parasitic capacitance associated with the multiplexer output pin and the input of the driver amplifier (around ~10pF), the sensor or circuit driving the inputs of the multiplexer must be relatively low impedance.  The design of figure 55 uses the high bandwidth amplifier (OPA320) driving the SAR ADC, and lower power, lower cost amplifiers driving the inputs of the multiplexer.  This design is able to settle when scanning through channels with an effective data rate of 10kSPS per channel (ADC is running at 80kSPS when converting 8 channels) while sampling DC Signals.

    Thank you and Best Regards,


  • Hi Luis

    Thanks a lot for your replying. Do you have some dedicated material that focus on the driving circuit design tips and notes for different kinds of ADC?