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ADC08500: ADC08500 CLK and DCLK Phase relation

Andreas Bozatzidis
Prodigy 20 points
Part Number: ADC08500

Dear support,

we have a design using an ADC08500 clocking at 250MHz the 2 parallel LVDS channels with the demux feature and capturing data inside an FPGA. We have logic inside the FPGA that needs to be clocked synchronously to the sampling frequency of 500MHz. Is it safe to clock this logic with the same clk input of the ADC? Is DCLK ADC out phase shifted with respect to clk input after the division by 2 and passing through the output clock generator?

Thank you in advance

  • 0
    TI__Mastermind 44290 points

    Hi Andreas

    I think it should be OK to clock your FPGA logic with a copy of the input CLK to the ADC.

    The output DCLK does have some logic delay (noted Tod in the datasheet, see Figure 5 and Figure 6). There will be some variation in Tod due to part to part variation as well as temperature and supply voltage. For that reason you will need to design your logic with some sort of FIFO mechanism to handle the potential skew variation between your clock at 500 MHz, with the DCLK running at 250 MHz (SDR Clocking).

    Please also note that during ADC power-up calibration and on-command calibration the output DCLK will be stopped, re-starting once the process has completed. Your data capture logic will also need to be tolerant of this behavior.

    Best regards,

    Jim B