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DAC38J84: No Output,Serdes PLL can not Locked

min hu
Intellectual 990 points
Part Number: DAC38J84
Other Parts Discussed in Thread: LMK04828,

DAC38J84

Mode 8411,sample clcok =2.5GHz, 4x interpolation, 8 lan.

the lan rate should be 6.25Gbaud,sample clock is external and CLOCK_PLL is power down.

'serdes_refclk_sel =1','serdes_refclk_div'=8,'MPY=10x=0010_1000','VRANGE=0','LB=00'

my start-up sequence:

1.power on;

2.provide dac_clk and sysref_clk;

3.write DAC spi registers as recomended(with 0x3B=0xB800, 0x3C=0x8050) and clear alarms;

4.read 'config 108(Addr=0x6C)',read out value'0x000F';

Why the serdes PLL can not locked?Any other registers I need to take care?

with the same configuration but lower clock rate to 2.4Ghz to avoid the upper limit of VCO 3.125GHz, I got the same result:read out value'0x000F';

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

parameter RATE = 2'b01;
parameter Serd_clk_sel = 1'b1;
parameter Serd_refckl_div = 4'b0011; //div4
parameter ENDIVCLK = 1'b1;
parameter LB = 2'b11; //High loop BW
parameter SLEEPPLL = 1'b0;
parameter VRANGE = 1'b0; //(1 below 2.17GHz)
parameter MPY = 8'b0001_0100; //5x

reg [REG_LEN-1:0] CFG_ROM [REG_NUM-1:0];


initial begin

CFG_ROM[00] = 24'h02_2083; //config2
CFG_ROM[01] = 24'h02_2082; //config2

CFG_ROM[02] = 24'h02_2082; //config2
CFG_ROM[03] = 24'h1A_0020; //config26
CFG_ROM[04] = 24'h31_1000; //config49
CFG_ROM[05] = 24'h32_0000; //config50
CFG_ROM[06] = 24'h33_0100; //config51
CFG_ROM[07] = {8'h3C,ENDIVCLK,2'b00,LB,SLEEPPLL,VRANGE,MPY,1'b0}; //config60:ENDIVCLK=1,LB=00,SLEEPPLL=0,VRANGE=0,MPY=0010_1000
CFG_ROM[08] = {8'h3B,Serd_clk_sel,Serd_refckl_div,11'b000_0000_0000}; //config59:serdes_clk_sel=1,serdes_refclk_div=7
CFG_ROM[09] = 24'h3D_0000; //config61
CFG_ROM[10] = {8'h3E,9'b0_0000_0000,RATE,5'b0_0000}; //config62:RATE=01(Half rate)
CFG_ROM[11] = 24'h3F_0000; //config63
CFG_ROM[12] = 24'h46_0120; //config70
CFG_ROM[13] = 24'h47_3450; //config71
CFG_ROM[14] = 24'h48_31C3; //config72
CFG_ROM[15] = 24'h49_0000; //config73
CFG_ROM[16] = 24'h4A_FF1E; //config74
CFG_ROM[17] = 24'h5F_0123; //config95
CFG_ROM[18] = 24'h60_4567; //config96
CFG_ROM[19] = 24'h25_8000; //config37
CFG_ROM[20] = 24'h24_0010; //config36
CFG_ROM[21] = 24'h00_0218; //config0
CFG_ROM[22] = 24'h03_F380; //config3
CFG_ROM[23] = 24'h4A_FF1E; //config74
CFG_ROM[24] = 24'h4B_0000; //config75
CFG_ROM[25] = 24'h4C_0F07; //config76
CFG_ROM[26] = 24'h4D_0300; //config77
CFG_ROM[27] = 24'h4E_0F0F; //config78
CFG_ROM[28] = 24'h4F_1CC1; //config79
CFG_ROM[29] = 24'h51_0000; //config81
CFG_ROM[30] = 24'h52_00FF; //config82
CFG_ROM[31] = 24'h54_0000; //config84
CFG_ROM[32] = 24'h55_00FF; //config85
CFG_ROM[33] = 24'h57_0000; //config87
CFG_ROM[34] = 24'h58_00FF; //config88
CFG_ROM[35] = 24'h5A_0000; //config90
CFG_ROM[36] = 24'h5B_00FF; //config91
CFG_ROM[37] = 24'h5C_1111; //config92
CFG_ROM[38] = 24'h5F_0123; //config95
CFG_ROM[39] = 24'h60_4567; //config96
CFG_ROM[40] = 24'h61_000F; //config97
CFG_ROM[41] = 24'h00_0218; //config0
CFG_ROM[42] = 24'h01_0003; //config1
CFG_ROM[43] = 24'h02_2082; //config2
CFG_ROM[44] = 24'h08_0000; //config8
CFG_ROM[45] = 24'h09_0000; //config9
CFG_ROM[46] = 24'h0A_0000; //config10
CFG_ROM[47] = 24'h0B_0000; //config11
CFG_ROM[48] = 24'h0C_0400; //config12
CFG_ROM[49] = 24'h0D_0400; //config13
CFG_ROM[50] = 24'h0E_0400; //config14
CFG_ROM[51] = 24'h0F_0400; //config15
CFG_ROM[52] = 24'h10_0000; //config16
CFG_ROM[53] = 24'h11_0000; //config17
CFG_ROM[54] = 24'h12_0000; //config18
CFG_ROM[55] = 24'h13_0000; //config19
CFG_ROM[56] = 24'h14_0000; //config20
CFG_ROM[57] = 24'h15_0000; //config21
CFG_ROM[58] = 24'h16_0000; //config22
CFG_ROM[59] = 24'h17_0000; //config23
CFG_ROM[60] = 24'h18_0000; //config24
CFG_ROM[61] = 24'h19_0000; //config25
CFG_ROM[62] = 24'h1E_1111; //config30
CFG_ROM[63] = 24'h1F_1111; //config31
CFG_ROM[64] = 24'h20_0000; //config32
CFG_ROM[65] = 24'h22_1B1B; //config34
CFG_ROM[66] = 24'h4A_0001; //config74
CFG_ROM[67] = 24'h03_F301; //config3

CFG_ROM[68] = 24'h64_0000; //config100 :clear ALARM
CFG_ROM[69] = 24'h65_0000; //config100 :clear ALARM
CFG_ROM[70] = 24'h66_0000; //config100 :clear ALARM
CFG_ROM[71] = 24'h67_0000; //config100 :clear ALARM
CFG_ROM[72] = 24'h68_0000; //config100 :clear ALARM
CFG_ROM[73] = 24'h69_0000; //config100 :clear ALARM
CFG_ROM[74] = 24'h6A_0000; //config100 :clear ALARM
CFG_ROM[75] = 24'h6B_0000; //config100 :clear ALARM
CFG_ROM[76] = 24'h6C_0000; //config100 :clear ALARM
CFG_ROM[77] = 24'h6D_0000; //config100 :clear ALARM

end // end initial

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

Thanks for any suggestion.

Hoo

  • 0
    Intellectual 990 points
    Serdes_PLL should be a Independent unit,it will not influeced by Lan_Errors or SYSREF_Errors or other Errors??
  • 0 in reply to min hu
    TI__Guru* 91947 points

    Min,

    We are looking into this.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Guru* 91947 points

    LMF_841_Fs_2p5GHz_Ext_Clk_PLL_Off.cfgDAC38J84_EXT_CLK_2p5G.pptxMin,

    I was able to duplicate your setup with no issues using the DAC38J84EVM with the TSW14J56EVM. I have attached two files. One shows all of the settings used by the DAC GUI and the other is the register configurations used by both the LMK04828 and the DAC. Compare these settings to what you have.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 990 points
    Hi,Jim

    select external clk,Serd_clk_sel =0,there is an error in FIG 56.
    I have checked the status of the Serdes Pll by driving SERDES PLL clock/80 to ALARM PIN.

    I set K=16 instead of 20 in your example,SYSREF = 19.53125.

    Q1:
    I notice clkjesd_div=8 in your example,what is the relationship between JESD clock and Sample clock??no details in datasheet.

    Q2:
    is there any way to map SYNC_n PIN function to ALARM PIN?? I made a mistake and leave SYNC_N_AB,SYNC_N_CD,and LVDS SYNC open in my PCB.TX block in FPGA can not receive the SYNC_n indication.

    Q3:
    Solved the Serdes PLL lock problem,here comes a new problem,there is a FIFO write_error,Reg 0x64 read out 0x0008.
    And still,DAC has No Output!
    SYSREF is continuous and provide the same time with 2.5GHz sample clock before DAC SPI configuration,And this matter??

    Looking forward to your reply,Thanks

    Hoo
  • 0 in reply to min hu
    TI__Guru* 91947 points
    Hoo,

    Are you saying that there is no SYNC connection between the DAC and your FPGA? Without this signal, the FPGA will never know when to start CGS and when to start ILA. You must have this connection or the link will never get established, and the DAC will never have an output.

    Regards,

    Jim
  • 0 in reply to jim s
    Intellectual 990 points

    Hi,Jim

    Yes,i made such a big mistake,NO SYNC between DAC and FPGA!

    Here is what i do:

    1) first: config DAC SPI registers,wait for a few second

    2) than: i try to manually send TX module a SYNC_n by VIO writting.  

    It shoulg be working??

  • 0 in reply to min hu
    TI__Guru* 91947 points

    Hoo,

    You can monitor the status of SYNC using the Alarm pin by setting bits 11:8 in Config27 to 0100 and set bit 4 to a "1" in Config0 to enable the Alarm pin. If the DAC passes CGS, you should see SYNC go from a low to high. Do you have access to the Alarm pin? If you see the SYNC transition from a low to high, this indicates the DAC has passed CGS and you would then need to de-assert SYNC going to the TX device. Since the ILA sequence will probably time out due to the fact you are changing SYNC manually, you will need to mask the ILA errors in the DAC, otherwise it will keep pulsing SYNC.  

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 990 points

    Hi,Jim

    Thanks,

    what is the JESD_CLK frequency related to sampling clock frequency or datarate??

    I would like to reduce serdes lans and change the mode to 4421:4Lan,2.5Gsps, 8x interpolation.data rate 312.5Msps.

    the serdes rate 6.25Gsps not changed,refclk=156.25MHz