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Original question:

DAC38J84: serdes pll out of lock

DAC38J84: serdes pll out of lock

Prasidh Ramabadran
Prodigy 50 points
Part Number: DAC38J84

Greetings,

I am using DAC38J84 EVM REV D to evaluate the DAC. I find that the output goes fully noisy probably due to SERDES PLL being out of lock whenever 8 SERDES lanes are are used. I need to operate the DAC at an input rate of 1000 MSPS for generation of DVB-S2X signals and am using an external clock and an interpolation rate of 1X. The EVM works fine at DAC input rates below 620 MSPS and while 4 SERDES lanes are used. I just used the 'Quick Start Menu ' on the GUI to configure the settings.  The settings on the quick start menu of  'DAC3XJ8X GUI V1.1' are as below:

EVM Clocking Mode: External Clock

Device: DAC38J84

Number of SerDes Lanes: 8

DAC Data Input Rate: 1000 MSPS

Interpolation: 1

DAC Output Rate:  1000 MSPS

FPGA Clock: 250 MHz

JESD204B Mode (LMFS) : 8411

SerDes Linerate: 10000 Mbps

Thanks and Warm Regards,

Prasidh

  • 0
    TI__Genius 9695 points
    Hi Prasidh,

    We will get back to you on this in a later post.

    Thanks,
    Eben.
  • 0
    TI__Guru 74179 points
    Prasidh,

    The better way to assist you is to provide a list of error codes that you can read back from the DAC38j84 GUI. Please advise the reason that you have determined SERDES PLL went unlock. Was this read back from the GUI?

    Please advise the test platform. This mode was verified on the TSW15j56 EVM + DAC38J84 EVM in the 8411 1x interpolation mode. Again, the error code will be assist the problem solving.

    You will also need to check your FPGA SERDES transmitter setting to see if you serdes transmitter has sufficient drive strength to reach out DAC. Our DAC has CTLE to compensate for some losses, but not major losses.
    You may also check the eye diagram of the DAC to see if there are signal integrity issue:
    www.ti.com/.../slaa762.pdf

    -Kang