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The ADS5263 has a SYNC pin, but I am not sure of the actual functionality of the pin. I have a customer that want to use the SYNC pin to synchronize (4) ADS5263’s. Here is the explanation of the application:
I've designed a board with (4) ads5263s on it. I want to sync the sampling of all 4 ADCs (16 channels). What I've done in the past with different multi-ADC chips is set all the chips to output a ramp (assuming that they all start the ramp at 0 at the same time - this is why my question is important), and delay the ramps from the different ADCs in an FPGA as required to being all of them into time alignment. Then I can switch the ADCs to output sample data, and all ADCS will be in sync.
I just looked again at the datasheet and it seems that the reset signal ONLY resets the serial interface, so it's useless to sync multiple ADCs. The only hope now is if the sync input resets the ramp counter. I have routed a signal from an FPGA to all sync inputs in parallel. The datasheet just says it's an "input signal to synchronize channels and chips when used with reduced output data rates." (Not a very detailed description of what it actually does.) I am using reduced data rates (4x bit clock).
Actually, since the sync signal is not sampled by the clock (at least, the datasheet doesn't say it is), it can't be used as a reliable way of sync'ing multiple chips due to its asynchronous nature.
Will the SYNC pin work in the described application? It is not very well described in the data sheet other than its use with CCD arrays. Can you explain the actual operate of the pin in terms of the question asked above by the customer?
Thanks for your help with this!
Richard Elmquist
