Other Parts Discussed in Thread: SN74AVC4T774
Hi,
Customer query below.
I’m just going over how we’re going to connect it to an FPGA. Unfortunately, the ADC08D502 seems to use quite non-standard input thresholds on the digital inputs:
Figure 1 - Extract from ADC datasheet
With a VA and VDR of 1.9V, this results in a VIH of 1.615 V and a VIL of 0.285 V. These fall way outside of the guaranteed 1.8 V LVCMOS output voltages used by the FPGA and all other devices I can find.
Figure 2 - Logic levels for 1.8V CMOS (From TI App note)
Do you have any suggestions on parts I can use as a buffer between the FPGA and the ADC to ensure correct levels are met?
Thanks,
Jani
