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Hello,
We have an issue with our design - spurs, which are an interger to ADS42JB49 actual sampling rate (CLKIN by Internal devider), are seen everyware on PCA. Additional coupling capacitors on power supply rails do not help. Does anybody have any suggestions?
Thank you in advance.
Vladimir,
Did you turn off SYSREF going to the ADC after the JESD link has been established? What is the frequency of the input clock? Is it filtered? What is sourcing it? What is the amplitude and frequency of the analog input? Is this signal filtered?
Regards,
Jim