Hello E2E,
We are using the ADS7887 on a design, and we are performing a timing analysis on the serial interface. The datasheet's test load for the timing spec is not clearly stated, and doesn't appear to match what is in the ibis model. The question is, what is the test load condition that was used to characterize the output timing for the serial data output pin?
I'm reluctant to "lead you down the path" to an answer at the risk that someone might gravitate towards an easy answer, but I'll take that chance if it potentially helps close this out more efficiently.
Typically a datasheet will explicitly identify the test conditions for which output pin timings are specified, test conditions that include a load circuit. Typically the device's IBIS model will include this test circuit inside, so long as it conforms to the simple topology the IBIS specification supports (VREF, RREF, CREF, and VMEAS).
In the case of this device, the datasheet does not explicitly identify the test load conditions used for specifying the output timing (of the serial data output pin). The serial data output's timing is specified via two parameters, one for the max delay and another for the min delay (output hold time). The output hold time spec includes a parenthetical note about a 50 pF load. Because this is only stated for the hold time spec and not the max delay spec, it begs the question as to whether it applies to the max delay spec or if a different load applies there.
Further complicating matters are the "REF" values in the IBIS model. A value of 50 ohms is assigned to RREF, along with a VREF of 1.65 V. That suggests that a 50 ohm termination to 1.65 V (VCC/2) is included in the test load, but no mention of this is made in the datasheet. We need the IBIS file to match the conditions that were used to specify the output timings in the datasheet to perform a specific type of simulation and analysis that allows us to compensate for the fact that our circuit load is (usually) different than the load used to characterize the device for its datasheet. We tried performing this analysis twice, once with the original value of 50 ohms in the IBIS file and again with this resistance changed to a very high impedance (representative of no significant resistive termination). The difference was huge, enough that in once case our system meets the timing requirements but fails timing in the other case.
To accurately complete this timing analysis and determine if we have to consider opening up a released design, we need to make sure the IBIS file, datasheet, and actual device characterization circuit are consistent. We can manually modify the IBIS file if necessary to get through the analysis in the short term if necessary, but we need to know what the test load circuit condition was.
Can you please comment on this?
Thank you very much,
Regards,
Russell
