Hello team,
Hope you are well. Can you provide some feedback on below questions:
Is there an IBIS AMI model for the highspeed pins on this part? This is a high speed DAC with a high speed clock and SYSREF along with JESD lanes.
Verifying our EE and PCB design with this DAC prior to producing the boards is important.
Can you point me to any model file from TI that will present expected loading found with the DACCLK, SYSREF and JESD lanes of the DAC38RF89?
