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Received email directly from Leo Zhao, need more information to confirmation the concern, will communicate by email and call.
Best regards
Dale Li
Leo:
Dale is clarifying a couple of points.
On the rising edge of CONVST, SDO becomes inactive, and goes to high-impedance state. Any data that has not been read at that time is lost. SDO does not become active again until after the new conversion data is latched into the output data buffer.
Also, after a conversion, care must be taken to allow sufficient acquisition time before initiating another conversion. According to the ADS8866 datasheet (p.3), 1200ns is the minimum acquisition time. Figure 40, on p. 16 of the datasheet shows a simplified diagram of the input circuit, where the CDAC is modeled as a single 55pF capacitor, and the on-resistance of the sampling switch is shown as a series 96-ohm resistor. This RC structure is the main reason why the acquisition time is needed. The input driver circuitry is another big factor as well, but that completely depends on each customer's implementation. (We can help with recommendations for drive circuits if need be.)
Acquisition time begins at the end of a conversion whether the data is clocked out or not. If you need to know exactly when that happens, this device has a BUSY indicator option.
When Dale and I were talking about your question, our concern about the accuracy of your second conversion came from the idea that you were going to trigger a conversion, then read out only part of the data before triggering a second one. Digitally, this is not a problem; you can ignore the data if you want to. However, if you do not have time to read all of the data, then you may not be leaving enough time for the analog input to settle. We just wanted to be sure you were thinking of that.
Let us know if this helps!