Other Parts Discussed in Thread: LMK04828,
Hi TI,
When running the TIDA-01021 and trying to set the LMK04828 to produce a continuous SYSREF signal I run into problems. PLL1 is programmed to produce a 100MHz signal from a 100MHz input reference (1:1) and PLL2 is programmet to produce a 2400MHz DEVCLK using VCO0. Both loops lock fine.
I hook up an oscilloscope to the J7 connector to watch the SDCLK13_N output. In the output section I set DCLK source to BYPASS and SDCLK source to Device clock. I can now view the 2400MHz signal on the scope.
The SYSREF section is set to continuos and the SYSREF divider to 240, which should produce a 10MHz signal. Toggling the SDCLK source to SYSREF, I now see an uneven pulse train with various pulse lengths (2.9ns, 6.4ns etc) - quite far from 10MHz. Trying other division values doesn't change much.
Switching back SDCLK source to Device Clock and now setting DCLK source to Divider, I can also see that the output section 1 to 32 DCLK divider is also not operating properly. It tries to divide, but some pulses get merged and prolonged in a seemingly random manner.
I have not yet worked with setting delays, SYNC et cetera, I thought I would start with getting this simple case to work first. I seem to be able to program all the other stuff to work, also the LMX2594s, so I don't think there's a signal integrity issue on the SPI interface side.
Am I missing something in the configuration, or is it some other issue? Below is the register code I have programmed into the LMX04828. Some comments relate to the code that was provided from TI.
Best regards,
Mats A
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LMK04828
0x000 0x90 % reset + disable 3wire SPI (?)
0x000 0x00 % resume
0x002 0x00 % normal op
0x003 0x06 %
0x004 0xD0 %
0x005 0x5B %
0x006 0x00 %
0x00C 0x51 %
0x00D 0x04 %
0x100 0x02 % DCLKout0=2
0x101 0x55 %
0x103 0x00 % ADLY=0, DCLKout0_MUX=DIV only
0x104 0x00 % SDCLKout1=DEVCLK
0x105 0x00 %
0x106 0xF0 % Delays PD, SDCLKout1 active
0x107 0x11 % LVDS
0x108 0x02 % DCLKout2=2
0x109 0x55 %
0x10B 0x02 % ADLY=0, DCLKout2_MUX=bypass
0x10C 0x00 % SDCLKout3=DEVCLK
0x10D 0x00 %
0x10E 0xF0 % Delays PD, SDCLKout3 active
0x10F 0x11 % LVDS
0x110 0x02 % DCLKout4=2
0x111 0x55 %
0x113 0x00 % ADLY=0, DCLKout4_MUX=DIV only
0x114 0x00 % SDCLKout5=DEVCLK
0x115 0x00 %
0x116 0xF0 % Delays PD, SDCLKout5 active
0x117 0x11 % LVDS
0x118 0x02 % DCLKout6=2
0x119 0x55 %
0x11B 0x00 % ADLY=0, DCLKout6_MUX=DIV only
0x11C 0x00 % SDCLKout7=DEVCLK
0x11D 0x00 %
0x11E 0xF0 % Delays PD, SDCLKout7 active
0x11F 0x11 % LVDS
0x120 0x02 % DCLKout8=2
0x121 0x55 %
0x123 0x00 % ADLY=0, DCLKout8_MUX=DIV only
0x124 0x00 % SDCLKout9=DEVCLK
0x125 0x00 %
0x126 0xF0 % Delays PD, SDCLKout9 active
0x127 0x11 % LVDS
0x128 0x02 % DCLKout10=2
0x129 0x55 %
0x12B 0x00 % ADLY=0, DCLKout10_MUX=DIV only
0x12C 0x00 % SDCLKout11=DEVCLK
0x12D 0x00 %
0x12E 0xF0 % Delays PD, SDCLKout11 active
0x12F 0x11 % LVDS
0x130 0x02 % DCLKout12=2
0x131 0x55 %
0x133 0x02 % ADLY=0, DCLKout12_MUX=bypass
0x134 0x20 % SDCLKout13=SYSREF
0x135 0x00 %
0x136 0xF0 % Delays PD, SDCLKout13 active
0x137 0x11 % LVDS
0x138 0x06 % VCO 0, buffered OSCin, OSCout=LVCMOS Norm/Inv
0x139 0x03 % SYSREF continuous
0x13A 0x00 % SYSREF_DIV=240
0x13B 0xF0 % SYSREF_DIV=240
0x13C 0x00 %
0x13D 0x08 %
0x13E 0x03 % SYSREF pulses=8
0x13F 0x00 % PLL2 N div input = presc, PLL1 N delay inp=OSCin, FB mux=PD
0x140 0x01 % SYSREF pulse=PD, all others ON
0x141 0x00 %
0x142 0x08 % DDLY step count=8
0x143 0x91 % SYSREF_CLR=1
0x143 0x11 % SYSREF_CLR=0, SYNC=EN, SYNC from SYNC pin
0x144 0x00 % enable all outputs SYNC (was 0xFF (?) )
0x145 0x7F % Fixed reg (was 00 (?) )
0x146 0x10 % Enable CLKin1, Inp buffer=bipolar
0x147 0x1B % CLKin1=manual, CLKin1_OUT_MUX=PLL1, CLKin0_OUT_MUX=off
0x148 0x02 %
0x149 0x02 %
0x14A 0x06 % RESET_MUX=low (0), RESET_TYPE=output open drain
0x14B 0x02 %
0x14C 0x00 %
0x14D 0x00 %
0x14E 0x00 %
0x14F 0x7F %
0x150 0x01 % holdover mode is active
0x151 0x02 %
0x152 0x00 %
0x153 0x00 % CLKin0 R counter [13:8]
0x154 0x78 % CLKin0 R counter [7:0]
0x155 0x00 % CLKin1 R counter [13:8], R=4
0x156 0x04 % CLKin1 R counter [7:0], R=4
0x157 0x00 % CLKin2 R counter [13:8]
0x158 0x78 % CLKin2 R counter [7:0]
0x159 0x00 % PLL1 N counter [13:8], N=4
0x15A 0x04 % PLL1 N counter [7:0], N=4
0x15B 0x14 % PLL1: WND=4ns, CPpol= active pos, CP gain 450uA
0x15C 0x20 % PLL1 DLD counter=32
0x15D 0x00 % PLL1 DLD counter=32
0x15E 0x00 % PLL1 R DLY=0, N DLY=0
0x15F 0x0D % PLL1 LD MUX = LD PLL1, output = open source (? datasheet and GUI not corresponding)
0x160 0x00 % PLL2 R counter [11:8], R=1
0x161 0x01 % PLL2 R counter [7:0], R=1
0x162 0x44 % PLL2 P=2, OSCin 63 to 127MHz, X2 disabled
0x163 0x00 %
0x164 0x00 %
0x165 0x0C %
0x171 0xAA % Fixed reg (says default 0x0A but program to 0xAA ?)
0x172 0x02 % Fixed reg
0x17C 0x15 % Optim VCO1 phase noise =LMK04828
0x17D 0x33 % Optim VCO1 phase noise =LMK04828
0x166 0x00 % PLL2 FCAL=dis, PLL2 N counter [17:16]
0x167 0x00 % PLL2 N counter [15:8]
0x168 0x0C % PLL2 N counter [7:0], N=12
0x169 0x59 % PLL2 CP gain etc. Bit 0 was 0, must be 1 acc to datasheet?
0x16A 0x20 % PLL2 DLD counter
0x16B 0x00 % PLL2 DLD counter
0x16C 0x00 % PLL2 loop filter R4=200R, R3=200R
0x16D 0x00 % PLL2 loop filter C4=10p, C3=10p
0x16E 0x15 % PLL2 LD MUX = LD PLL2, output = open source (? datasheet and GUI not corresponding)
0x173 0x00 % PLL2 normal OP
