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LM98714: LM98714 reset timing and SPI slew rate criteria

Alex Wu1
Intellectual 360 points
Part Number: LM98714

Hello Expert.

Could you help to provide spec of LM98714
1. reset Timing spec
2. SPI slew rate criteria on different CLK frequesncy.

  • 0
    TI__Expert 6330 points
    Hi Alex,

    Allow me to contact the engineer assigned to this product. Expect an answer by 3/13.

    Regards,
    Aaron
  • 0
    TI__Expert 4940 points
    Hi Alex,

    I'll answer your questions early next week, it will be based on bench analysis since these are non-spec items .

    Regards,
    Costin
  • 0 in reply to Costin Cazana
    Intellectual 360 points

    Hi Costin

    Do you have the result of reset timing and SPI slew rate criteria on bench analysis.

    Best Regards,

    Alex

  • 0 in reply to Alex Wu1
    TI__Expert 4940 points

    Hi Alex,

    LM98714 SPI has been designed for fast clock, frequencies up to the main clock-INCLK.

    For fast SPI clock, external SPI driver should not violate the spec set-up and hold time.

    If the drive SCLK Tr/Tf is very slow and main clock is off, SPI will not work.

    With main clock( INCLK) On , SPI works according to spec up to at least Tr/Tf=400nS.

    My recommendations:

    1) Fast SPI clock: Tsetup>4nS, Thold>1nS

    2) For very slow SPI clock: Tr/Tf<=100nS.

    3) INCLK should be on all the time: Fspi<Finclk and the time between two SPI transactions should be >4xTinclk

    4) What RESET non spec parameter you need: the min RESET width?

    Thank you,

    Costin

  • 0 in reply to Costin Cazana
    Intellectual 360 points

    Hi Costin

    Please also provide the following specifications of LM98714

    1.Reset time range of pin 5(reset)(min~max time).

    2.LVDS output voltage range(min~max)

    3.LVDS CLK(TXCLK) Tr/Tf range(min~max times)

    4.LVDS TX data output :base on LVDS CLK 16.65MHz each time spec(min~max time) of Txpp0~Txpp6, there is only typ value with VLDS CLK 45MHz in datasheet.

    Best Regards,

    Alex

  • 0 in reply to Alex Wu1
    TI__Expert 4940 points

    Hi Alex,

    These are not spec parameters, I'll reply next week based on bench analysis

    Regards,

    Costin

  • 0 in reply to Alex Wu1
    TI__Expert 4940 points

    Hi Alex,

    1. This is a non spec parameter. My recommendation is min reset time at least 4 INCLK. That's no max time limitation.

    2.This is a spec parameter: LVDS Output: Min=180mV, Max=450mV with Rl=100ohm

    3. TXCLK Tr/Tf is affected by external conditions: Tline impedance and losses and receiver load. Based on estimation and bench measurements for a good matched system fastest Tr/Tf is a least 1nS. My recommendation is not to slow it down  more than 1/3 of LVDS Data bit cell(TXCLK/7)

    4.Datasheet has typ values for the toughest conditions at the highest freq. The internal delays will have a smaller impact at lower freq(16.65MHz), all these timings are percentage wise  much close to the ideal transition: N*TXCLK_period /7 where N is the data bit order.

    Regards,

    Costin

    Costin