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ADS54J42: ADS54J42 SNR?

Part Number: ADS54J42
Other Parts Discussed in Thread: DAC3482, ADS54J40

Dears.

We are developing ADS54J42.


We have an ADS54J42 problem on the board.

Band Width : 60Mhz,

LMFS=2242

Decimation : 2

Lane Rate : 5.5Gbps


We need help and solutions.

The figure below shows the ADS54J42 ADC input with matlab captured by FPGA.
The ADC clock is 276.48MHz and the IF is 207.36MHz Center.
The difference (-6.9) - (-60.1) = 53.2 is about 18MHz from the center when singleton is input.

The figure below shows the ADS54J42 input looped to the DAC3482 and measured using the MXA.
At 18MHz from the center, the difference is 53.3.
The data sheet(14page) is about 70.
What's the problem?
Problems with ADS54J42 configuration?

Thank you.

  • Henry,

    In this mode, you need to select either low pass filter mode or high pass filter mode. In each case, your signal of interest (207.36MHz) will fall in the transition band. See the attached file for more info regarding this. You also have a wrong lane rate. It should be 2.7648Gbps with this setup. I have also attached the ADC config file I used for this setup. The plots show that when using the high pass filter mode with your setup, the usable bandwidth is between roughly 139MHz and 202MHz. If it is critical that you be able to sample data at 207.36MHz, you will have to change your sample rate.

    Regards

    Jim

    ADS54J42_Fs_276.48MHz_LMFS_2242.pptxADS54J40_2x_dec_highpass_2242.cfg

       

  • Henry,
    I have sent your question over to an engineer that will take a look at it.
    Regards,
    Brian
  • Dears.

    We have an ADS54J42 problem on the board.
    The exact conditions of our test results are as follows.
    We need CFG file support.

    Band Width : 120Mhz,
    Lane rate : 5.5296bps
    ADC data rate : 276.48MHz
    Fs : 552.96MHz
    Fin : 207.36MHz
    LMFS : 2242
    DEC : 2x
    DEC FILTER : LPF

    Register Value
    6900
    01 32
    00 80
    06 0F
    31 0A
    32 0A

    6800
    4D 80
    41 12
    52 81
    72 08
    44 3E

    Thank you
  • ADS54J40_2x_dec_lowpass_4222_Fs_552.96M.cfgHenry,

    The attached config file works with the TI EVM using your settings.

    Regards,

    Jim

  • DEAR.JIM

    Loading a CFG file from ADS54J42EVM will not PLL lock it.

    Should I use the ADS54J40_2x_4222 file in HSDC-Pro?

    The test results are as follows.

    Our LMFS is 2242.

    Can you support HSDC ADS54J40_2x_2242 files?

     

    The difference between the SNR and EVM values of the document.

    The figure below is based on the guide document.

    EVM LOAD

    "LMK_Config_Onboard_614p4_VCO1"

    "ADS54J40_LMF_8224"

    Test Source is 187.5Mhz, 8dBm.

    SNR is not 70dBFs.

    Why does it differ from the Datasheet?

    The test results are as follows.

    Thank you

  • Henry,

    I may have sent you the wrong file. If you still plan on using the settings sent to us shown below, please try the config file attached.

    Band Width : 120Mhz,
    Lane rate : 5.5296bps
    ADC data rate : 276.48MHz
    Fs : 552.96MHz
    Fin : 207.36MHz
    LMFS : 2242
    DEC : 2x
    DEC FILTER : LPF

    Regards,

    Jim

    ADS54J40_2x_dec_lowpass_2242.cfg

  • Dear.JIM
    You need an HSDC-Pro file to test the attached file.
    I do not have 2242.ini in HSDC-Pro.
    I need an HSDC-Pro file to test the attached file.
    Please tell me how to test.
    Thank you.
  • 6082.ADS54J42_LMFS_2242.zipHenry,

    Files are attached.

    Regards,

    Jim

  • Dear. JIm

    We input 187.5 MHz and 8 dBm into the ADC with the signal generator.

    SNR does not appear in customer Board, as shown in Figure 10 of the datasheet.

    Our SNR is 55dbfs.

    What is the solution?

    Thank you

  • Henry,

    Is this still an issue? If so and it is a custom board, can you send the schematic so we can take a look at it?

    Regards,

    Jim