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i config ads54j42 as below:
//reset device
ad_spi_write_dw(0x0000,0x81);/// Internal software reset, clears back to 0
ad_spi_write_dw(0x4001,0x00);///Clear any unwanted content from the unused pages of the JESD bank.
ad_spi_write_dw(0x4002,0x00);///Clear any unwanted content from the unused pages of the JESD bank.
ad_spi_write_dw(0x4003,0x00);/// sel main digital page
ad_spi_write_dw(0x4004,0x68);/// sel main digital page
ad_spi_write_dw(0x60f7,0x01);///reset digital block
ad_spi_write_dw(0x6000,0x01);///Pulse the PULSE RESET bit (so that register writes to the main digital page go into effect).
ad_spi_write_dw(0x6000,0x00);///Pulse the PULSE RESET bit (so that register writes to the main digital page go into effect).
//perfermence modes
ad_spi_write_dw(0x0011,0x80);///Select the master page of the analog bank.
ad_spi_write_dw(0x0059,0x20);///Set the ALWAYS WRITE 1 bit.
ad_spi_write_dw(0x0039,0x00);///ad sample fre <400 ,set 0
ad_spi_write_dw(0x003a,0x00);///ad sample fre <400 ,set 0
ad_spi_write_dw(0x0056,0x00);///ad sample fre <400 ,set 0
//programe desired register
ad_spi_write_dw(0x4003,0x00);///sel jesd digital page
ad_spi_write_dw(0x4004,0x69);///sel jesd digital page
ad_spi_write_dw(0x6000,0x80);///bit[7]:ctrl K,bit[4]:test mode en bit[0]: ila-----------------------------------------
//analog bank jesd link config
ad_spi_write_dw(0x6016,0x90);///bit[7]: must write 1,bit[4]:Lane sharing is enabled, both channels share one lane(LMFS = 1241)
ad_spi_write_dw(0x6031,0x0A);///DA bus order
ad_spi_write_dw(0x6032,0x0A);///DB bus order
ad_spi_write_dw(0x6001,0x22);///jesd register 01
ad_spi_write_dw(0x4003,0x00);///sel jesd anolog page
ad_spi_write_dw(0x4004,0x6a);///sel jesd anolog page
ad_spi_write_dw(0x6016,0x02);///pll mode 40X mode
ad_spi_write_dw(0x6017,0x40);///The PLL RESET bit is pulsed
ad_spi_write_dw(0x6017,0x00);///The PLL RESET bit is pulsed ,0 --1 -- 0
ad_spi_write_dw(0x4003,0x00);/// sel main digital page
ad_spi_write_dw(0x4004,0x68);/// sel main digital page
ad_spi_write_dw(0x604d,0x08);///decimation enable
ad_spi_write_dw(0x6041,0x10);///DECFIL EN = 1 ,The DECFIL MODE[3:0] ,41 register bit5 = 0 and bit[2:0] = 000 ,bit 3 must 0
ad_spi_write_dw(0x6052,0x80);///ddc mode only must write bit7 1
ad_spi_write_dw(0x6072,0x08);///ddc mode only must write bit3 1
ad_spi_write_dw(0x6000,0x01);///Pulse the PULSE RESET register bit. All settings programmed in the main digital page take effect only after this bit is pulsed
ad_spi_write_dw(0x6000,0x00);///Pulse the PULSE RESET register bit. All settings programmed in the main digital page take effect only after this bit is pulsed
ad_spi_write_dw(0x4003,0x00);///sel jesd digital page
ad_spi_write_dw(0x4004,0x69);///sel jesd digital page
ad_spi_write_dw(0x6006,0x08);///set K
but ad sample sin wave ,but sample data is wrong, pls help me to chack config reg ,thanks so much.
