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TSW14J56EVM: ADC14X250

Part Number: TSW14J56EVM

Hi,

I am using TSW14J56EVM with ADC14X250EVM as instructed in document SLAU625, however, my final goal is to use ADC14X250 to send data to a FPGA using JESD204B over a single lane.

The questions that I have are as follows:

1. The serialized data sent from ADC14X250, SO+/SO- have SYSREF and clock information, why is redundant clock information sent to TSW14J56EVM over the FMC connector?

2. The FPGA used in TSW14J56 - Aterra Arria V GZ, is this compatible with JESD204B, or does it contain deserializer for JESD204B type signals?

3. Will the setup shown in SLAU625 figure 2 work if I do not send the separate clock and SYSREF signals?

4. Is it even possible to establish JESD204B communication over 1 lane using ADC14X250? If so, what do I do with the Sync signal? Is there any TI recommended FPGA evaluation board for this particular purpose?

Thanks in advance for your help.

  • Lizon,

    We are looking into this.

    Regards,

    Jim

  • Hi,
    #1: The standard requires it. To my knowledge, SO+/- doesn't embed sysref. CDR in the receiver (FPGA) can recover the clock from the incoming data stream. However, it still needs a clock to derive the frame rate of the data on the link.
    #2: I'm not sure about this. I'll check with the team and update you.
    #3: You'll need to provide a clock and sysref as required in SLAU625.
    #4: Yes and L (of LMFS) will be 1 in this case. This is a single channel ADC with one (differential) serdes lane.
    Regards,
    satish.

  • Hi,
    An update on #2:
    Altera Arria V GZ used in TSW14J56 is compatible with JESD204B standard as mentioned in page 5 of the Altera JESD204B IP User Guide
    www.altera.com/.../ug_jesd204b.pdf
    This has been implemented in TSW14J56revD firmware
    Regards,
    satish.