Part Number: TSW14J56EVM
Hi,
I am using TSW14J56EVM with ADC14X250EVM as instructed in document SLAU625, however, my final goal is to use ADC14X250 to send data to a FPGA using JESD204B over a single lane.
The questions that I have are as follows:
1. The serialized data sent from ADC14X250, SO+/SO- have SYSREF and clock information, why is redundant clock information sent to TSW14J56EVM over the FMC connector?
2. The FPGA used in TSW14J56 - Aterra Arria V GZ, is this compatible with JESD204B, or does it contain deserializer for JESD204B type signals?
3. Will the setup shown in SLAU625 figure 2 work if I do not send the separate clock and SYSREF signals?
4. Is it even possible to establish JESD204B communication over 1 lane using ADC14X250? If so, what do I do with the Sync signal? Is there any TI recommended FPGA evaluation board for this particular purpose?
Thanks in advance for your help.
