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ADS7040: SDO read by DSP

Part Number: ADS7040



My customer chosen ADS7040 first time. ( ES coming soon )

This is the question about SDO read from customer's DSP( C6745).


We see following description in the data sheet 8.3.4 Serial Interface.

The first zero is launched on the SDO pin on the CS falling edge. Subsequent bits

(starting with another 0 followed by the conversion result) are launched on the

SDO pin on subsequent SCLK falling edges.

The SDO output remains low after 10 SCLKs.

A CS rising edge ends the frame and brings the serial data bus to 3-state.



Question : Is following sequence correct for reading data by DSP?

*DSP should read data  by rising edge of SCLK.

*read data using  a first rising edge of SCLK from CS=L ,to subsequent 9 rising edge ;total 10 rising edge.


I had attached ppt file for our understanding.


Best Regards





  • Hello Kanji San

    I have gone through the attached timing diagram.

    If your customer is expecting very low delays in communication path from host MCU to ADC then customer can latch the data on the clock rising edge as shown in the presentation

    If customer expects delay due to long trace length or parasitic on the board then it is recommended to latch the data on the falling edge of the clock.

    I would recommend to probe CS, SCLK and SDO on the MCU side to see how much delay is introduced in the circuit and then latch the data to the respective edge to get valid ADC result.

    Let me know if you have any additional questions

    Thanks & Regards
  • Hello Abhijeet san

    Thank you for your answer immediately!

    I understood that.