ADS4222: which clock buffer to work with?

Andrew,

(1) the recommend input clock amplitude for LVDS is 0.7Vpp, LVPECL is 1.6Vpp. what does this meant? differential typical voltage?

This is the differential swing about the common mode of the signal when using that standard.

(2)  what is VODH and VODL logic for this ADC? where to find it, thanks.

This can be found on page 10. VHL = DRVDD - 0.1V (Min)   and  DRVDD (TYP).      VLO = 0V (TYP)  and 0.1V (Max)

(3) Is CDCLVD1204, CDCLVD1213 and CDCLVD2102 all suitable to drive?

Yes. Follow the termination example shown in Figure 161 if you are driving the input clock from an LVDS source, like the CDCLVD1204. 

Regards,

Jim

Jim thank you for fast response!
For (1) where I don't understand is, CDCLVD1204 for example, the LVDS VOD (Differential output voltage magnitude) max is 450mV, min is 250mV. How to link with ADS4222 clock input range for LVDS, thank you!!

Andrew