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ADS1298: Problem reading register from SPI

luis juarez
Prodigy 140 points
Part Number: ADS1298

Im working with ADS 1298 and NRF52832 from Nordic, i have a problem when i tried to read the ID control register( 00H ), i just get random values, maybe the problem is the SPI between the ADS and NRF52, i test the SPI of the NRF with arduino and it works well, i used 128Khz for the test, whit the ads i used 128K,250K,500K,1M,2M,4M,8M and its the same, i tried to read the ID control register before configure any other register.  Can you help me?

what is the frequency of the SCLK? would  i have to wait every byte that i send or recieve?

  • 0
    TI__Mastermind 48570 points
    Hi Luis,

    Thanks for your post and welcome to the forum!

    Can you provide an example of these random values?

    The timing requirements for the serial interface can be seen in section 7.6 of the datasheet and the minimum SCLK period is 50nS. However this will be dependent on your sampling speed. This can be seen in section 9.5.1.2 of the datasheet which covers the SCLK.
  • 0 in reply to Alexander Smith
    Prodigy 140 points
    Thank you for fast answer, sometimes i get 00h (the most of times), c2h, 35h,e6h,06h.
    Sorry i dont speak english, with "what is the frequency of the SCLK?" i meant wich is the recommended frequency for SCLK if i don't configure any registers yet? i just want to read ID register to know the SPI works.
  • 0 in reply to luis juarez
    TI__Mastermind 48570 points

    Hi Luis,

    My apologies, I didn't understand what you meant.

    Since SCLK is supplied by an external source the ADS1298 does not have a recommended SCLK frequency, rather it has minimum and maximum acceptable SCLK frequency limits based on the data mode and the number of channels being read.

    The minimum SCLK speed in RDATAC mode can be calculated as fDATA * (n+1) * 24, where n is the number of channels. For 5 channels at 8 kSPS, you need a minimum SCLK frequency of 1.152 MHz. You should run the SCLK a little faster than that in order to account for the required timing specifications outlined on page 17.

    For the minimum SCLK speed In RDATA mode, you must account for one extra byte when calculating the minimum SCLK frequency, assuming you wish to read every sample. The minimum SCLK frequency for 8 kSPS will be (RDATA + STATUS + n*24)bits * 8e3 = 1.216 MHz. However, RDATA allows you to read the most recent conversion on-demand and you do not have to read every sample. If your SPI transaction overlaps the next sample, the data will not be corrupted.

    Please see equation 7 in the datasheet: tSCLK < (tDR – 4tCLK) / (NBITS × NCHANNELS + 24) to adjust the speed to your system. 

    The maximum SCLK speed depends on the applied DVDD voltage. For DVDD between 2.7 and 3.6VDC, the fastest SCLK you can use is 20MHz (50ns period). Below 2.7V, the SCLK is limited to a period of 66.6ns or approximately 15MHz.

  • 0 in reply to Alexander Smith
    Prodigy 140 points
    thank you, i can use SPI interface now :)