In its datasheet there writes 0.7 Vpp nominal for LVDS for CLK input pins. Can we drive these pins through a standard LVDS, HR pins of ultrascale+ familiy FPGAs, configuring pins as LVDS ?
In ADC322x EVM they had used a 1:4 transformer before CLK input pins, do we need to use this structure before connecting to a standard LVDS?
regards,
serkan
