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ADS114S06B: unexpected MISO line behaviour

Catalin Popa
Prodigy 85 points
Part Number: ADS114S06B

Hello,

setup:

- 5V to 3.3V logic level shifter as depicted in "bidirectional converter" - https://jeelabs.org/book/1504d/

- Arduino UNO

- Arduino IDE 182

- TQFP to100 mil adapter PCB

- No 47 Ohm resistors; the rest identical to figure 94 of "ADS114S0xB Low-Power, Low-Noise, Highly Integrated, 6- and 12-Channel, 4-kSPS, 16-Bit, Delta-Sigma ADC With PGA and Voltage Reference" document

- SPI.beginTransaction(SPISettings (20000000, MSBFIRST, SPI_MODE1)); // 2 MHz clock

tried: 

- RREG-ing 15 registers as below:

addr = B00100000; //
aux = 0; //
// data = 0xFF;
int c = 0xF;
while (c-- != 0)
{
data = SPI.transfer16((uint16_t) (addr + c << 8 | aux));
// delay(1);
data = SPI.transfer(0x00);
// data = SPI.transfer(0x00);

Serial.print("Devie ID: ");
Serial.println(data);

SPI_next_byte();
}

- RREGing from 0h and 4h

- inserting a 47 Ohm resistor close to the ADC part for the MISO line

results:

- See attached

question:

- why does the SPI compatible part not yield a SPI compatible result ?

Thanks you,

Praveen

Dinesh

Yours trully

Patel

  • 0
    TI__Guru** 113765 points
    Hi Catalin,

    Welcome to the E2E forum! I have a couple of questions. The first is if you have tried toggling CS? It is possible that an incomplete or noisy transmission has put the SPI internals in an unexpected state. Toggling CS will reset the SPI communication so that it is in a known state. If you wish to control CS, it must remain low throughout the entire communications transaction.

    Also, what is the state of the RESET pin? This must be pulled high and not left floating.

    Third, why do you need to use a level shifter? IOVDD can go to 5V if that is what the micro is using. There are three supplies required for the ADS114S06B. The analog supply (AVDD/AVSS) the digital core supply (DVDD) and the IO supply for the digital communications interface (IOVDD). All three supplies must be operating or the device will stay in a reset state. IOVDD and DVDD can be the same voltage up to 3.6V, however if needed IOVDD can go all the way to 5V, so there is no need for a level shifter on the digital output signals.

    Best regards,
    Bob B
  • 0 in reply to Bob Benjamin
    Prodigy 85 points

    That wast fast!

    Yes, sorry, the !CS is being used as part of the SPI protocol (i.e. not tied to GND but toggled). The !RESET is kept high as it should.

    I have taken out the level shifter - missed that part. It now behaves as below.

    I am going to check the voltage levels again.

    Thanks,

    Catalin

  • 0 in reply to Catalin Popa
    TI__Guru** 113765 points

    Hi Catalin,

    I'm a little confused by what I see.  Your MISO line changes outside of the SCLK region.  Are you sure you are connected to the proper pin(s)?

    You may also just want to make sure your device is out of the reset condition by setting the START pin high and checking DRDY to see if it is toggling at the default rate of 20sps (50ms period).  If you do not see this happening, then the device is still held in a reset condition by either the RESET pin not truly high, or not all the supplies are present at the device.

    If DRDY is toggling as expected, then you should be able to read the registers.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 85 points

    hello Mr. Bob,

    I have done some adjustments to the IOVDD supply voltage: put it to 5V from the previous 3.3V. Also tried resetting it after power up:

      digitalWrite(PIN_RES, LOW);
  delayMicroseconds(2);
  digitalWrite(PIN_RES, HIGH);
  delay(2);                                     // delay until our ADC resumes after a reset (max 4096 * t_clk)

  digitalWrite(PIN_NSEL, LOW);

    And quite a few rewirings and resoldering. The thing started budging.

    >>by setting the START pin high and checking DRDY to see if it is toggling at the default rate of 20sps (50ms period).  If you do not see this happening

    I can see that happening. Following are various voltages:

    DVDD - DGND:               3.32V

    IOVDD - DGND:              4.84V

    AVDD - AVSS:                 4.84V

    !RESET - DGND:            4.83V

    START/SYNC - DGND:  4.84V

    CLK - DGND:                  0V

    REFOUT - DGND:          0V

    REFCOM - DGND:         0V 

    DOUT/!DRDY - DGND: 3.2V when a logic analyzer probe is connected or 0.1V when not (idle SPI)

    SCLK - DGND:               0V  (idle SPI)

    DIN - DGND:                  0V   (idle SPI)

    Help! Thanks!

  • 0 in reply to Catalin Popa
    TI__Guru** 113765 points
    Hi Catalin,

    It might help to follow the Saleae shots if you turn off the I2C protocal analyzer as this is confusing things a bit. One thing I noticed is CS goes low and the first MOSI data sent to the ADS114S06B is 0x0E. This is an invalid command. Make sure that the commands being sent are valid and what you are intending to send is what is actually being sent.

    For 0x0E, what are you attempting to do or read at this point?

    Best regards,
    Bob B
  • 0 in reply to Bob Benjamin
    Prodigy 85 points
    I am so ashamed... just figured I'd throw in a couple of addresses to read from but neglected the actual RREG command. The thing is finally talking to me. Yay!!