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ADS131E08S: Data rate / sample frequency and output rate

TISL
Expert 4375 points
Part Number: ADS131E08S

Dear e2e Support,

Just to avoid any confusion on our ADS131E08S:

Could you confirm that when we are talking about a max data rate @64ksps it's related to the sample frequency of all ADCs?

Should we take care of specific calculation on the SPI output rate?

The customer needs, here, are to acquire 8 channels at 16ksps, with 16bits or more; using additional PGAs on our inputs.

Regards,

  • 0
    TI__Guru 64186 points

    Hello TISL,

    Thank you for your post.

    Yes, the same data rate setting is applied to all 8 channels in the ADS131E08S. This device is a simultaneous-sampling ADC.

    The calculation to determine the minimum SPI clock frequency is the same (see equation 7 on page 27).

    The 64 kSPS and 32 kSPS data rates output data in 16-bit format. The remaining data rate options use 24-bit format.

    Best Regards,

  • 0 in reply to Ryan Andrews
    Prodigy 20 points
    If I understand you correctly, if I want to sample all 8 channels at 16 kSPS/24bits, will I get 128 kSPS ? Is the chip data throughput sufficient to output all channels at maximum sample rate ?

    Regards,
    Jean
  • 0 in reply to Jean THOMAS
    TI__Guru 64186 points

    Hello Jean,

    The 8 channels are sampling in parallel. There are 8 independent, simultaneous-sampling ADC cores in the ADS131E08S and each channel will have a new conversion available at the same time.

    The throughput will depend on the number of enabled channels, the data rate, and the data resolution (16 or 24 bits). In order to read the the 24-bit STATUS word and data from all channels before the next conversion is complete, your SCLK frequency will need to be at least = Data Rate x [24 + 8 * (n bits / channel)].

    Best Regards,