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ADS8900B: No. of SCLK in SPI format

Isao Takigasaki
Expert 3350 points
Part Number: ADS8900B

Hi,
My customer have a question.

In table 6 of the datasheet of ADS8900, No. of SCLK is 20, but Figure 60 shows 22 CLKs.  Which is correct, 20 CLKs or 22 CLKs?  If 20 CLKs is corrrect, does SDO packet starts from D19 in Figure 60 ?

Similarly, In table 7, No. of SCLK is 5 in quad mode, but we can see 6CLKs in the packet for quad mode in Figure 66.  Which is correct, 5 CLKs or 6 CLKs?  If 5 CLKs correct, Don't the D21 and D20 exist in the packet of Figure 66 and Is the MSB D19?

Best Regards, Taki

  • 0
    TI__Mastermind 46360 points
    Hello,

    The ADS8900B allows a minimum of 20 SCLKs for a 20b data read. The first 20 bits shifted out of the ADS8900B are the conversion result. If you do not need the parity bits, you can pull /CS high to end the data transfer frame after 20 SCLKS. If you need to update a command register during a transfer Frame, then you need to clock at least 22 SCLK's for the full command word, but if you just want to transfer a conversion result (read only) and do not need the parity bits, you can do this in 20 SCLKs.

    Referring to your question and Figure 60, the 20b SDO conversion result is located in D21 through D2; D1 and D0 are the parity bits.

    Conversion bit 19 (MSB) -> D21
    Conversion bit 18 -> D20
    .................................
    Conversion bit 1 -> D3
    Conversion bit 0 (LSB) -> D2
    Parity bit 1 -> D1
    Parity bit 0 -> D0

    It is a similar situation in SPI quad mode. If you need the parity bits, then you need 6 SCLKs, the first 5 SCLK's clock out the 20b conversion result, and the 6th SCLK clocks out the 2 parity bits plus two 'zero's', for a total of 24bits (22 ignoring the two additional 'zero' bits). If you do not need the parity bits, then you can clock the 20b conversion result in 5 SCLKs.

    Please let me know if this is not clear or if you have more questions.

    Regards,
    Keith N.
    Precision ADC Applications
  • 0 in reply to Keith Nicholas
    Intellectual 895 points

    Hi Keith,

    I have a doubt, usually SPI is a byte protocol right? Then how to bring the CS to high at 5th or 6th clock pulse? Is there any option to modify the IP of SPI in the host IC? or is there any option to write the logic in FPGA? Please notify if any IP is available for xilinx FPGA regarding this eSPI.

    Please help me to understand. Please correct me if I misunderstood

    Thanks,

  • 0 in reply to Venkatesh P17
    TI__Mastermind 46360 points
    Hello,

    This will depend on the specific features of the host processor used. The same for an FPGA if you are using a standard IP library. In either case, you can provide additional clocks to maintain byte wide transfers to support existing protocols.

    Regards,
    Keith