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Original question:

DAC37J84: LVPECL termination for Clock and Sysref

DAC37J84: DAC37J84: LVPECL termination for Clock and Sysref

Kiran VG
Intellectual 530 points
Part Number: DAC37J84
Other Parts Discussed in Thread: LMK04828, DAC38J84

Hi Jim and Neeraj,

I checked the schematic and there is no resistor divider network other than 121ohm terminations on the clock lines.

As mentioned previously R179 & R180 are used as 121ohm terminations on the DAC Clock lines after LMK04828. Then you have a capacitor in series and feeding into DAC Clock pins. There is no resistor network to bring down the Vout of 1.7Vpp of LMK04828 LVPECL level to 0.8Vpp required by DAC.

DAC specification clearly mentions that VIDpp for Clock should be 800mV.

Does this mean that Clock-P can have 800mV swing and Clock-N can have 800mV swing so that total differential input is 1.6Vpp?

Please clarify about it.

Regards,

Kiran

  • 0
    TI__Guru 66184 points

    Hello Kiran,

    The 0.8Vpp specification of the DAC38j84 clock input is a typical recommended clock swing for optimal SNR/SFDR. It is defined as differential (P - N leg) swing. 

    This specification is the same as the VOD specification of the LMK04828 (see figure 9 for VOD definition). 

    The standard LVPECL termination (121ohm pull-down) is sufficient for the application, and also, you have to compensate for PCB loss and potentially clock filter loss and reflections. Hence, the swing required at the clock driver side may need to be slightly higher depending on PCB design.

    See below specification of LVPECL for VOD specification. 

  • 0 in reply to Kang Hsia
    Intellectual 530 points

    Thanks Kang Hsia for the clarification.