ADS1298R: DRDY signal ceases to generate

Hi Ninad,

Welcome to our e2e forum! As noted in the original post on the ADS1298, are you reading out the data between DRDY pulses, ensuring that your SCLK is fast enough to retrieve all of the conversion results? The DRDY output will go high with the first SCLK after you start reading the conversion results. It should return low once the next conversion sample set or ready to be retrieved. Can you provide register details and post a scope or logic analyzer screen shot showing your communication sequence and perhaps a schematic showing your ADS1298 connections?

ADS1298-breakout.schHere I have attached the schematic file of the board.

I have ensured that my SCLK is fast enough to not mess up the DRDY timing, DRDY is 500SPS and SCLK is fast enough to comfortably read 27 bytes of data from the ADS.

Register initializations:

ADS_WREG(ADS1298_CONFIG1_REG, 0x06);		//Data Rate = Fmod/1024, Low Power Mode
ADS_WREG(ADS1298_CONFIG2_REG, 0x10);		//Test signals are generated internally
ADS_WREG(ADS1298_CONFIG3_REG, 0xD4);		//PD_REFBUF enable, VREFP is set to 2.4V, RLD_REF is set, RLD_REF is fed externally, RLD_BUF enabled, RLD_sense is off, RLD is connected
ADS_WREG(ADS1298_LOFF_REG, 0x02);		//Do not use
ADS_WREG(ADS1298_CH1SET_REG, 0x50);		//Gain = 8, Normal electrode input
ADS_WREG(ADS1298_CH2SET_REG, 0x50);
ADS_WREG(ADS1298_CH3SET_REG, 0x50);
ADS_WREG(ADS1298_CH4SET_REG, 0x50);
ADS_WREG(ADS1298_CH5SET_REG, 0x55);		//Gain = 8, Test signals
ADS_WREG(ADS1298_CH6SET_REG, 0x55);
ADS_WREG(ADS1298_CH7SET_REG, 0x65);		//Gain = 12, Test signals
ADS_WREG(ADS1298_CH8SET_REG, 0x65);
ADS_WREG(ADS1298_RLDSENSP_REG, 0x00);	
ADS_WREG(ADS1298_RLDSENSN_REG, 0x00);
ADS_WREG(ADS1298_LOFFSENSP_REG, 0x00);
ADS_WREG(ADS1298_LOFFSENSN_REG, 0x00);
ADS_WREG(ADS1298_LOFFFLIP_REG, 0x00);
ADS_WREG(ADS1298_GPIO_REG, 0x00);		//GPIO OUTPUT
ADS_WREG(ADS1298_PACE_REG, 0X00);
ADS_WREG(ADS1298_RESP_REG, 0XF0);		// Respiration phase = 90, Internal Respiration of with user generated signals
ADS_WREG(ADS1298_CONFIG4_REG, 0X00);		//64 kHz modulation clock
ADS_WREG(ADS1298_WCT1_REG, 0x00);
ADS_WREG(ADS1298_WCT2_REG, 0x00);

I am sorry, I dont have any images of waveforms!

One more detail that i think may be of interest is that - When i initialize the ADS, VCAP1 capacitor charges to about 1.019V no matter how much delay I set in the code. Only when I start reading and DRDY halts, VCAP1 voltage exceeds 1.1V (as i observed in the datasheet). Can this be the issue?

ADS1298_STM32.pdf

Sorry about the schematic. I have uploaded the schematic pdf file!

More development on my problem is that when I changed some capacitors (prescribed in the datasheet) DRDY pin does toggle, data does come. But the problem still intermittently persists.

So i am guessing that it is a problem with the interfacing Capacitors and Resistors. can you please point out if there are some Caps (or Res) whose prescribed values have to be stringently be followed?

Answering your question, the voltage at VCAP1 pin reaches about 1.161V

Please inform me if the pdf file still doesnt open, and i am attaching the schematic again.7142.ADS1298-breakout.sch

Oh yeah, and the two links don't seem to be the issue in my case!
The MCU side seems to be okay in terms of sending signals and processing data.

Glad to hear that you're making progress!

Which caps did you change?

VCAP1 should be 22uF, not 1uF as per the Pin Function section of the datasheet.

Any patterns that suggest a root cause of the intermittent data stream?

Are your digital traces from the device to the MCU a reasonable length?