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DAC8806: The reset pin has caused my driver to fail.

Doug Smyth
Prodigy 220 points
Part Number: DAC8806

I am driving my DAC8806 with an FPGA at 3.3v. Last week a GPIO pin on the FPGA quit working. It is connected directly to pin28(reset) on the DAC8806. I thought nothing of it as the FPGA has gone through a year of testing. I replaced the FPGA and through some more use, the same pin on the FPGA went bad in one day. That run on my PCB goes from pin to pin with no vias.

My configuration is as follows, I have a THS4011 connected directly to the DAC8806 as per your PDF. The THS4011( at -9v to +9v) then drives a OPA552(-9v to +40v). It all looks good under Tina.

VREF on the DAC8806 is -9v.

My goal is to generate what looks like a modified version of the upper part of a 0-30v sine wave or "mountain range". Since I can code 0V, do I really need the reset pin?

Do you have any idea as to why the DAC8806 kills my GPIO pin? I looked at it with an O-scope. and there is a little jitter at that pin when I turn the system on and off.

At $100 each for the FPGA, it can get expensive.

Thanks.

Regards,

Doug

  • 0
    TI__Guru 53283 points
    Hi Doug,

    The pin should be high impedance and should not cause any damage to the FPGA. What could protentially cause problems is that if the FPGA is powered before the DAC and it drives the pin high, the ESD protection diode may turn on. This would look like a diode to ground (or whatever the potential of VDD is at at the time). This can cause the GPIO pin to go into short circuit condition.

    I would advice you check the power on sequence and confirm if the FPGA is trying to drive the pin before the VDD on the DAC8806 is established. Or, if it is easier and you are not using it, just tie RST to VDD and disconnect it from the FPGA. Optionally you could add a series resistor between the GPIO and the RST pin, maybe 5-10kΩ, which would limit and current in a transient state.

    Thanks,
    Paul
  • 0 in reply to Paul_Frost
    Prodigy 220 points
    Thank you very much. I had the opamps on a separate switch. The 3.3v and (-9v, +9v, +40v) were effectively on two different switches.
    They are now on a single relay. I will also instruct my FPGA to start all pins at 0v for a several hundred ms. The next revision will also have a series resistor.
    Thanks again.
    Doug