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DAC38RF89: Firmware for TSW14J56

Jonathan Kolbrak
Intellectual 460 points
Part Number: DAC38RF89

Hello, we are running the DAC38RF89 using the TSW14J56.  We have the evaluation setup running and working well.  We'd like to verify the operation when using GPIO0 as the SYNC pin.  This doesn't seem to be working with the standard firmware build.  Is it possible to get a build or the source code to modify the firmware to use the GPIO0 pin.

Regards,

Jon

  • 0
    TI__Guru 67904 points

    Hi,

    You may go to the following website and click on the following to download the TSW14J56 Firmware source code:

    -Kang

  • 0 in reply to Kang Hsia
    Intellectual 460 points
    Kang,

    Thank you, we've got the firmware folks looking at this.

    Does the DSW14J56 default to looking at the SYNC0+/- pins and not the GPIO0 pin for a SYNC signal from a DAC? Is there another way besides updating the source code to make it look at the GPIO0 or GPIO1 pins?

    Jon
  • 0 in reply to Jonathan Kolbrak
    TI__Guru 67904 points
    Jon,

    The default is LVDS based SYNC input for the FPGA. I am not aware of the configuration to make it accept CMOS based input. This may require change in firmware option on our side as well.
    -Kang
  • 0 in reply to Kang Hsia
    Intellectual 460 points
    Kang,

    Thank you for the quick responses. So is the firmware that is available on the website what we would need to update to implement this kind of option or is there another part of the firmware that would have to be updated?
  • 0 in reply to Jonathan Kolbrak
    TI__Guru 67904 points

    Hello Jonathan,

    sorry for the confusion. If you intend to use the HSDC PRO software and the DAC38RF89 EVM, then I believe the firmware modification may have to come from our side. I am not sure if there are additional hooks that the team need to consider to change the mod. However, this is not going to be a quick effort (requires justifications, budget, planning, and engineering time, etc). Since the intention of the HSDC PRO software is to get your evaluation going, I do not suggest going through this route. I recommend evaluating the DAC38RF89 EVM as is with the LVDS input option for the FPGA. If your project really require such option, then I will have to find out what is necessary for the change, and we may have to discuss this offline (for justification to our management). 

    The firmware design file that you downloaded from the web is intended for you to re-use in your own PCB design and implementation. You may re-use the project and change the LVDS option to CMOS option to interface with the DAC38RF89 on your own board. It is a good reference design for the Altera FPGA that you may re-use to speed up your engineering time.

    -Kang

  • 0 in reply to Kang Hsia
    Intellectual 460 points

    Kang,

    I agree with your response.  Thank you for the clarification.  We will update and test this on our own design.

    Thanks,

    Jonathan