Hello team,
I have an application where, in order to time everything correctly, I will have to violate tSCCS, and I'm curious to understand the ramifications of doing so.
My theory is that the tSCCS spec applies to the write register command and most likely to the other commands. However, when reading data (in RDATAC mode), as long as the micro can latch the data before DOUT goes high impedance, raising the chip select early should not cause any problems as the chip does not have a command to decode. What are your thoughts on this theory? Any concerns about the chip operation that I am missing?
As another data point, I ran a test with a single ADS1298 where I reduced the tSCCS time from 3 us to 0.25 us for only the SPI data reads in “read continuous” mode. The ADS1298 was configured for 2000 Hz ODR and measuring MVDD on each channel. The SPI clock was 4 MHz. I placed data value checks on the status word and channel eight (top 11 bits). I ran this test for 8 minutes and did not see any data corruption. This seems to support my theory, but again my testing is limited and I would like your expert feedback.
Thanks,
Brian
