Other Parts Discussed in Thread: ADS54J20,
When using FPGA to configure the register of ADS54J20, SPI timing sequence was normal, SCK frequency was 1MHz, register readback was normal when configuring analog Bank, SPI cannot read back when configuring JESD Bank. it seems that the SPI link is OK. the analog bank is working properly.
Is there anyother hardware issues caused this error ? different power supply ? or anyother configuration error?
thank you and looking forward to your reply ASAP.