ADS7029-Q1: Delay time: SCLK falling to (next) data valid on DOUT

Hi Cynthia-san,

I'm sorry for rate reply.
I have additional questions.

Q1
The timing diagram of the ADS786x is attached below.



Does the ADS7029-Q1 have a hold time?
(This is the value described as tH (SCLKF-SDOVALID) in the timing diagram.)
Please let me know as a reference value.

Q2
Is tD_CKDO not dependent on the SCLK frequency?
For example, is tD_CKDO max 25ns when SCLK is 1MHz?

Q3
Since tD_CKDO is max 25 ns, I understand that SCLK max is 40MHz.
is it correct?

Best regards,
Yuto Sakai

Yuto-san

Unfortunately we do not specify the holding time, but the tD_CKDO is not dependent on the SCLK frequency. as for your example, if SCLK is 1MHz, tD_CKDO will still have a max of 25ns.

As for your last question. What SCLK frequency are you trying to use? Do you need max throughput of 2MSPS?

If you are trying to read the SDO at the rising edge of SCLK, then due to the delay of 25ns, the max SCLK used to ensure proper reading is <20MHz

25nsx2 = 50ns, then 1/50ns= 20MHz max SCLK frequency

I would suggest reading at the falling edge.

Regards

Cynthia

Hi Cynthia-san,

Thank you for your reply.
I'm sorry for bothering you.


Figure 1 Please check the timing diagram.
For example, the data read on the falling edge of SCLK "3" is "D7", right?

Also, I understand that the delay from the reading of “D7” at the falling edge to the activation of “D6” is tD_CKDO, which is max 25 ns.
Is it correct?

Best regards,
Yuto Sakai

Correct, your understanding is correct

Hi Cynthia-san,

Thank you for your reply.
Can you give me your opinion on the min value of td-CK-DO?
It does not have to be a guaranteed value.

Best regards,
Yuto Sakai

This is a large span, it could fall anywhere really

It is not zero, but it can be near zero, say 2.5ns, 5 ns, perhaps in that range

But each part can vary widely within the specification

Hi Cyntia-san,

Thank you for your kind support.
The questions of our customers have been resolved.

The questions of our customers have been resolved.
There are additional questions about "the max value of td-CK-DO (25 ns)".
Does not change max25ns even if SCLK is lower frequency (for example 10MHz)? 
Does DOUT (SDO) detect the falling edge of SCLK and start data transition?
Attach my image of the operation.

Best regards,
Yuto Sakai

Unfortunely, the image you attached did not go through correctly. If you would like, please try again

But to address your concern, the Max time td-CK-DO (25 ns) does not decrease even if SCLK frequency is decreased. The tD_CKDO is not dependent on the SCLK frequency.

If you are using a 10MHz frequency clock. A period is 100ns long and starts at the falling edge. After 25ns seconds delay from the falling edge, the new SDO data will be available.

The rising edge will be at half a period, at 50ns. Because the rising edge is beyond the max 25ns, then the data at the rising edge will be valid.

In short, at 10MHz, the rising edge of SCLK can be used to read the data.

You can also read the SDO data at the falling edge no matter what the SCLK is used.  When doing this though , note that you are reading the previous data and not the new data at the falling edge.

Regards

Cynthia