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Im trying to realize a 10 bit 50MS/s SAR type ADC using an industry standard simulation tool in 65nm node. There seems to be a problem with the setup and hold violations. The individual blocks seems to be working fine but the problem comes when i integrate and run the simulations at the top level. Sounds strange but the output seems to be not seen. Can i get some help on this??
PS: I have double and triple checked my connections from time and again but seems like i have stuck on this regard.
Hi Sumukh,
Is there a particular TI device/part number that you are working with here? If so, please provide the detail and we'll get you to the right support team. This forum is not geared towards simulation and top level ADC design questions.