Im trying to realize a 10 bit 50MS/s SAR type ADC using an industry standard simulation tool in 65nm node. There seems to be a problem with the setup and hold violations. The individual blocks seems to be working fine but the problem comes when i integrate and run the simulations at the top level. Sounds strange but the output seems to be not seen. Can i get some help on this??
PS: I have double and triple checked my connections from time and again but seems like i have stuck on this regard.
